STM32U575 Clock Configuration Confusion

[ScottD]

I have a custom board that I am getting ready to program that is using the STM32U575. I am a little confused about the clock configuration. My board has an external 32768 crystal. I am not sure I have the MX program clock configuration correct. I want the internal clocks running at full 160mhz speed with the internal clocks calibrated by the external 32768. Below is a screen shot from the MX clock configuration. I think I might not have the settings correct. Could you please check the configuration to see if I am configuring the clocks correctly.

A second minor question that I am confuzzled about. I noticed the code generated by MX program initializes SysTick. Is that the same as the SysClk?

[MHank.1]

Although for a different processor this article may help you.

ARM Tutorial Part 1 Clocks 

[TDK]

> I want the internal clocks running at full 160mhz speed with the internal clocks calibrated by the external 32768.

There is no automatic calibration of the internal clocks to the LSE clock. If you need an accurate clock, use an HSE crystal or clock as a source.

You are using the HSI as a clock, which is okay but not super accurate. See details in the datasheet. Generally +/- 1% or so.

You can adjust the HSI by applying a trim value, but it's never going to be as accurate as an external crystal.

> I noticed the code generated by MX program initializes SysTick. Is that the same as the SysClk?

SysTick and SYSCLK are different, they have no relation to each other.

SysTick is an interrupt that happens every 1 ms (typically) and is used by HAL to keep track of time. SYSCLK is an internal clock that gets fed to HCLK before the prescaler.

[ScottD]

The following is from the STM32U5 Users Manual. This seems to say that the clocks can be synchronized against the LSE. Am I misunderstanding what it states?

Hardware auto calibration with LSE (PLL-mode)

When a 32.768 kHz external oscillator is
present in the application, it is possible to
configure either the MSIS or the MSIK in a
PLL-mode. This mode is enabled:

• for MSIS by setting MSIPLLEN with MSIPLLSEL = 1 in RCC_CR
• for MSIK by setting MSIPLLEN with MSIPLLSEL = 0

In case MSIS and MSIK ranges are generated from
the same MSIRC source, the PLL-mode is applied
on both MSIS and MSIK. When configured in
PLL-mode, the MSIS or MSIK automatically
calibrates itself thanks to the LSE. This mode
is available for all MSI frequency ranges. At
48 MHz, the MSIK in PLL-mode can be used for
the OTG_FS, or the USB, avoiding the need of an
external high-speed crystal. If LSE clocks
pulses are stopped, the MSI PLL-mode is
automatically unlocked, and the MSI accuracy is
consequently degraded. On all STM32U5 devices
except STM32U575/585 rev. X, the MSI PLL-mode
unlock event is connected to an EXTI line: this
is used to generate an event or interrupt
supporting wake-up from Stop 0, Stop 1, or Stop
2 mode (see Table 118: Interrupt sources and
control and Table 187: EXTI line connections).