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nethecite
Associate II
November 20, 2024
Question

STM32U5 - does OctoSPI support inter-byte spacing?

  • November 20, 2024
  • 7 replies
  • 1362 views

Hi there,

I'm working on a project with the STM32U5. This MCU comes with both a SPI and a OCTOSPI peripheral.

The SPI peripheral supports a setting called MasterInterDataIdleness - in the reference manual it's shown as "master Inter-Data Idleness", which inserts "idle" (zero) clock cycles between two consecutive data frames.

Does the OctoSPI peripheral support this setting as well, when configured for 2-lane SPI? I couldn't find any mention of it.

Thanks in advance.

This topic has been closed for replies.

7 replies

KDJEM.1
KDJEM.1
ST Technical Moderator
November 21, 2024

Hello @nethecite and welcome in the Community,

 

For the OCTOSPI interface, the chip-select high time CSHT[5:0] represents the period between two
successive operations in which the memory is deselected.  This time must be configured according to the device datasheet. So, it can be used to specify the minimum number of CLK cycles for which the NCS must remain high. Please see RM0456. 

KDJEM1_0-1732193429836.png

 

For more information please take a look at AN5050 5.2 OCTOSPI/HSPI/XSPI configuration for Regular-command
protocol  section and Overall FAQs for QUADSPI/OCTOSPI/HSPI/XSPI "1.6. How to calculate the chip select high time".

Thank you.

Kaouthar

 

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netheciteAuthor
Associate II
November 21, 2024

Thank you KDJEM.1 for trying to help. It looks like you may have misunderstood me: I'm interested in inserting clock cycle spacing (i.e. a "zero" at length of 1 clock cycle or more) between consecutive bytes, not between operations.

netheciteAuthor
Associate II
November 21, 2024

I'm unfortunately stuck with using the OctoSPI peripheral due to overlooking this inter-byte spacing requirement when designing the hardware. I'd like to try to dive deeper into your suggestion of a software-based delay.

A straightforward approach would be to "hack" a delay into the OctoSPI driver after it finishes transmitting each byte.

Is there a way to do it with DMA as well?

Open to hearing suggestions if anyone has them.

Appreciate your help.

Tesla DeLorean
Tesla DeLorean
Guru
November 21, 2024

There's some FIFO / buffering action going on in there.

For DMA you'd have to pace the dispatch through a TIM rather than the QSPI/OSPI peripheral directly.

Or stuff patterns into the buffer. Or change width to get the bits vs slack clocks in the right ratio

Alternately you could perhaps bit-bang-blast via a TIM+DMA+GPIO->BSRR

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netheciteAuthor
Associate II
November 21, 2024
@Tesla DeLorean wrote:

For DMA you'd have to pace the dispatch through a TIM rather than the QSPI/OSPI peripheral directly.

Yes, maybe set the TIM to trigger DMA (single byte transmission) every (8+1) SPI clock cycles, so that it will transmit the byte, and then delay for an additional clock cycle before the next one

 

@Tesla DeLorean wrote:

Or stuff patterns into the buffer.

Or change width to get the bits vs slack clocks in the right ratio

Can you please elaborate? How will patterns help, if I need the clock to be 0 (low) between bytes?

And regarding changing the width, is that in DMA or in OctoSPI?

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