STM32U5 - does OctoSPI support inter-byte spacing?

[nethecite]

Hi there,

I'm working on a project with the STM32U5. This MCU comes with both a SPI and a OCTOSPI peripheral.

The SPI peripheral supports a setting called MasterInterDataIdleness - in the reference manual it's shown as "master Inter-Data Idleness", which inserts "idle" (zero) clock cycles between two consecutive data frames.

Does the OctoSPI peripheral support this setting as well, when configured for 2-lane SPI? I couldn't find any mention of it.

Thanks in advance.

[KDJEM.1]

Hello @nethecite and welcome in the Community,

For the OCTOSPI interface, the chip-select high time CSHT[5:0] represents the period between two
successive operations in which the memory is deselected.  This time must be configured according to the device datasheet. So, it can be used to specify the minimum number of CLK cycles for which the NCS must remain high. Please see RM0456. 

For more information please take a look at AN5050 5.2 OCTOSPI/HSPI/XSPI configuration for Regular-command
protocol  section and Overall FAQs for QUADSPI/OCTOSPI/HSPI/XSPI "1.6. How to calculate the chip select high time".

Thank you.

Kaouthar

[nethecite]

Thank you KDJEM.1 for trying to help. It looks like you may have misunderstood me: I'm interested in inserting clock cycle spacing (i.e. a "zero" at length of 1 clock cycle or more) between consecutive bytes, not between operations.

[nethecite]

I'm unfortunately stuck with using the OctoSPI peripheral due to overlooking this inter-byte spacing requirement when designing the hardware. I'd like to try to dive deeper into your suggestion of a software-based delay.

A straightforward approach would be to "hack" a delay into the OctoSPI driver after it finishes transmitting each byte.

Is there a way to do it with DMA as well?

Open to hearing suggestions if anyone has them.

Appreciate your help.

[Tesla DeLorean]

There's some FIFO / buffering action going on in there.

For DMA you'd have to pace the dispatch through a TIM rather than the QSPI/OSPI peripheral directly.

Or stuff patterns into the buffer. Or change width to get the bits vs slack clocks in the right ratio

Alternately you could perhaps bit-bang-blast via a TIM+DMA+GPIO->BSRR

[nethecite]

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@Tesla DeLorean wrote:

For DMA you'd have to pace the dispatch through a TIM rather than the QSPI/OSPI peripheral directly.

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Yes, maybe set the TIM to trigger DMA (single byte transmission) every (8+1) SPI clock cycles, so that it will transmit the byte, and then delay for an additional clock cycle before the next one

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@Tesla DeLorean wrote:

Or stuff patterns into the buffer.

Or change width to get the bits vs slack clocks in the right ratio

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Can you please elaborate? How will patterns help, if I need the clock to be 0 (low) between bytes?

And regarding changing the width, is that in DMA or in OctoSPI?

[Tesla DeLorean]

"which inserts clock cycles between two consecutive data frames"

I'm not familiar with your unspecified hardware, you indicated initially you wanted "clock cycles"
inserted, not suppressed.

In Dual Bit, you'd get 4 clock cycles per byte,  for 2 clocks you'd need to go into Quad Bit, and arrange the pattern so the least 2-bit of each nibble carried the data you want across the bus to something wanting 2-bits. Yes you'd need to cook the data first, but then it's an efficiency tradeoff vs bit banging or whatever to support your hardware.

How much data are we talking about?

[nethecite]

Thank you, Tesla DeLorean. I should have been clearer in my original post, and I will edit it. I meant that I need to insert "idle" (zero) clock cycle between bytes, like below:

(Which is a feature that is offered by the SPI peripheral via MasterInterDataIdleness, but not the OctoSPI peripheral).

I now understand what you meant by arranging patterns, but that will probably not help with inserting "idle" clock cycles.

You also mentioned changing the width to get the bits vs slack clocks in the right ratio - can you elaborate?

The amount of data I'd like to send, with OctoSPI using 2 lanes (to emulate a MOSI and a MISO), is about 50-100 bytes. It's not too much, but will be done very frequently, so if there's a workaround that can use DMA I'd be very interested!