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nethecite · 2024-11-20

Hi there,I'm working on a project with the STM32U5. This MCU comes with both a SPI and a OCTOSPI peripheral.The SPI peripheral supports a setting called MasterInterDataIdleness - in the reference manual it's shown as "master Inter-Data Idleness", whi...

nethecite · 2024-11-21

Thank you, Tesla DeLorean. I should have been clearer in my original post, and I will edit it. I meant that I need to insert "idle" (zero) clock cycle between bytes, like below:(Which is a feature that is offered by the SPI peripheral via MasterInter...

nethecite · 2024-11-21

@Tesla DeLorean wrote:For DMA you'd have to pace the dispatch through a TIM rather than the QSPI/OSPI peripheral directly.Yes, maybe set the TIM to trigger DMA (single byte transmission) every (8+1) SPI clock cycles, so that it will transmit the byte...

nethecite · 2024-11-21

I'm unfortunately stuck with using the OctoSPI peripheral due to overlooking this inter-byte spacing requirement when designing the hardware. I'd like to try to dive deeper into your suggestion of a software-based delay. A straightforward approach wo...

nethecite · 2024-11-21

Thank you KDJEM.1 for trying to help. It looks like you may have misunderstood me: I'm interested in inserting clock cycle spacing (i.e. a "zero" at length of 1 clock cycle or more) between consecutive bytes, not between operations.

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STM32U5 - does OctoSPI support inter-byte spacing?

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Re: STM32U5 - does OctoSPI support inter-byte spacing?

Re: STM32U5 - does OctoSPI support inter-byte spacing?

Re: STM32U5 - does OctoSPI support inter-byte spacing?