Hi there,
I'm working on a project with the STM32U5. This MCU comes with both a SPI and a OCTOSPI peripheral.
The SPI peripheral supports a setting called MasterInterDataIdleness - in the reference manual it's shown as "master Inter-Data Idleness", which inserts clock cycles between two consecutive data frames.
Does the OctoSPI peripheral support this setting as well, when configured for 2-lane SPI? I couldn't find any mention of it.
Thanks in advance.
