2024-08-29 01:30 AM - last edited on 2024-08-29 03:24 AM by SofLit
The reference manual RM0503 rev2 has inconsistent information about the flash wait states.
Table 9 in §3.3.4 shows three options: 0WS, 1WS, 2WS (and, by the way, it says that all three of them correspond to "1 CPU cycle", which seems wrong).
Instead, §3.7.1 (description of the FLASH_ACR register) indicates only two options for the LATENCY[2:0] field: 000 zero wait states, 001 one wait state.
Which is correct?
Solved! Go to Solution.
2024-08-30 04:58 AM
Hello @SZano ,
Getting back to you regarding this issue in the documentation after getting the internal feedback.
There are three options: 0WS, 1WS, 2WS.
So, two points to be fixed:
- Section 3.7.1 FLASH access control register (FLASH_ACR) will be fixed to show the value of 2WS.
- Table 9: CPU cycle numbers.
2024-08-29 03:27 AM - edited 2024-08-29 03:37 AM
Hello @SZano ,
Will check internally and get back to you.
Internal ticket number 189757 not accessible by the community users.
2024-08-30 04:58 AM
Hello @SZano ,
Getting back to you regarding this issue in the documentation after getting the internal feedback.
There are three options: 0WS, 1WS, 2WS.
So, two points to be fixed:
- Section 3.7.1 FLASH access control register (FLASH_ACR) will be fixed to show the value of 2WS.
- Table 9: CPU cycle numbers.