2022-07-11 05:56 AM
Hello,
I have a STM32L152RE and I use PA1 (Pin type is FT 5v tolerant) as ADC_IN1. Vdd is 3.3V and the voltage on PA1 usually is around 5V and sometimes it drops to 2.5V ( when I need to take the measure).
Several comments on various blog said that usually is not possible have voltages above 4V even if the pin is FT if the pin is used as ADC. I searched everywhere in the datasheet and there is any note for the STM32L152RE. So I'd like to know if I can apply safely 5V on that pin.
Regards,
Riccardo
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2022-07-11 08:24 AM
The GPIOs are only 5V tolerant when used as digital inputs.
In analogue mode, the pin is no longer 5V tolerant because of (unspecified) parasitic pn junctions to VDDA.
When the analogue input function is activated on the GPIO, the maximum input voltage on the GPIO pin must not exceed VDDA or VREF+ (whichever is smaller) by more than 0.3V.
Does it answer your question?
Regards
/Peter
2022-07-11 08:24 AM
The GPIOs are only 5V tolerant when used as digital inputs.
In analogue mode, the pin is no longer 5V tolerant because of (unspecified) parasitic pn junctions to VDDA.
When the analogue input function is activated on the GPIO, the maximum input voltage on the GPIO pin must not exceed VDDA or VREF+ (whichever is smaller) by more than 0.3V.
Does it answer your question?
Regards
/Peter
2022-07-11 08:24 AM
Hi Ricardo,
I do agree that the tolerance behavior when the pin is connected to the ADC is not highlighted in the documentation. When the pin is connected to the ADC, any voltage on this pin above VDD might lead to unpredictable behavior.
By the way, the reference manual states " ADC input range: VREF– ≤ VIN ≤ VREF+" and (VREF+ < VDDA) (note that for STM32L1 family VDDA must be roughly equal to VDD).
So you should disconnect the pin to the ADC when the input is above VDD.... but of course to achieve this you need to know, which, depending on your application, might not be obvious.
For your information, in a similar way, the Five Volt Tolerance of a pin is also lost if you select the internal pull-up on the pin, but in that case it is more easy to understand (see figure Basic structure of a five-volt tolerant I/O port bit).
Br,
Jacky
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2022-07-11 09:06 AM
@Peter BENSCH , @JBURB ,
> When the pin is connected to the ADC, any voltage on this pin above VDD might lead to unpredictable behavior.
And damage, or not?
Can this fact please be explicitly given in ALL datasheets? It is for example given in DS for 'F407 as
5. FT = 5 V tolerant except when in analog mode or oscillator mode (for PC14, PC15, PH0 and PH1).
footnote to the pinout table. It would be nice if this would be consistent across the datasheets, this question is quite often asked here.
[shameless self-advertisement] Could you please comment on this writeup? [/shameless self-advertisement]
JW
2022-07-11 12:17 PM
Perfect thanks. Unfortunately there isn't any note on the datasheet.
2022-07-12 05:18 AM
Hello,
Thank you in advance for your input and remarks regarding our documentation improvement.
In the meantime, you could refer to AN4899 "STM32 microcontroller GPIO hardware settings and low-power consumption" , there is a dedicated chapter : 5.2.2 Five-volt tolerant GPIO (FT) which is explaining that :
Please feel free if you have any further remark or question about this topic.
Have a nice day,
Regards,
Simon
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2022-07-12 05:36 AM
Hi Simon,
Thank you for the comments.
Maybe the datasheets could refer to AN4899 in this regard, too.
> a GPIO is five-volt tolerant only in input mode.
What about open-drain output with no pullup enabled?
> If some analog input function is enabled on the GPIO (ADC input active, COMP input, OPAMP input),
What about the oscillator pins? These are not enabled in GPIO, and they are also probably not related to VREF+.
> then the maximum operating voltage on pin cannot exceed min(VDDA, VREF+) + 0.3 V.
Does the positive injection limit, given in DS for TT pins, refer to all these cases (i.e. FT in analog mode, FT as output with switched-on high-side output transistor(s)) , too?
Thanks,
Jan
@Simon V.