2020-03-20 05:20 AM
Hello,
I am having a bit of a problem with using the ADC on the STM32L072 in combination with the External Trigger and the DMA.
I have just two conversions set not continuous mode and not discontinuous, but the DMA is set to take 32 results.
If I trigger by software, then it neatly converts the two channels and put the results in the buffer. When it hits the End of Sequence ISR the START bit is clear.
If I trigger the ADC start from the timer it keeps going with the conversions, filling the buffer and in the End of Sequence interrupt the START bit is still set.
Faulty setup:
ADC
ISR 0x00000000
IER 0x00000008
ADRDYIE 0
EOSMPIE 0
EOCIE 0
EOSIE 1
OVRIE 0
AWDIE 0
EOCALIE 0
CR 0x10000001
ADEN 1
ADDIS 0
ADSTART 0
ADSTP 0
ADVREGEN 1
ADCAL 0
CFGR1 0x00000881
AWDCH 0x00
AWDEN 0
AWDSGL 0
DISCEN 0
AUTOFF 0
AUTDLY 0
CONT 0
OVRMOD 0
EXTEN 0x2
EXTSEL 0x2
ALIGN 0
RES 0x0
SCANDIR 0
DMACFG 0
DMAEN 1
CFGR2 0x80000000
OVSE 0
OVSR 0x0
OVSS 0x0
TOVS 0
CKMODE 0x2
SMPR 0x00000005
SMPR 0x5
TR 0x0fff0000
HT 0xfff
LT 0x000
CHSELR 0x00000003
CHSEL18 0
CHSEL17 0
CHSEL16 0
CHSEL15 0
CHSEL14 0
CHSEL13 0
CHSEL12 0
CHSEL11 0
CHSEL10 0
CHSEL9 0
CHSEL8 0
CHSEL7 0
CHSEL6 0
CHSEL5 0
CHSEL4 0
CHSEL3 0
CHSEL2 0
CHSEL1 1
CHSEL0 1
DR 0x00000041
CALFACT 0x00000041
CCR 0x00c00000
PRESC 0x0
VREFEN 1
TSEN 1
LFMEN 0
DMA1
ISR 0x00000000
CCR1 0x000025a1
MEM2MEM 0
PL 0x2
MSIZE 0x1
PSIZE 0x1
MINC 1
PINC 0
CIRC 1
DIR 0
TEIE 0
HTIE 0
TCIE 0
EN 1
CNDTR1 0x00000020
CPAR1 0x40012440
CMAR1 0x200007a0
If I just clear the EXTEN and EXTSEL in ADC1.CFGR1, then it behaves as I extpect.
Any suggestions why the timer keeps triggering conversions even though it shouldn't?
Cheers,
Ed.
2020-03-20 05:13 PM
> Any suggestions why the timer keeps triggering conversions even though it shouldn't?
Why it shouldn't? Is it set to one-pulse mode?
JW
2020-03-23 03:59 AM
The timer is free running and is synchronised to an external clock.
I only want it to trigger the ADC once. In the setup above both DISCEN and CONT are set to zero so I would expect the ADC to disable itself (clear the START bit) at the end of the conversion sequence.
Cheers,
Ed.
2020-03-23 10:55 AM
From the current data sheet (DocID025941 Rev 5):
"When hardware trigger is selected in single mode (CONT=0 and EXTEN = 01), ADSTART is not cleared by hardware when the EOS flag is set. This avoids the need for software having to set the ADSTART bit again and ensures the next trigger event is not missed."
Which implies that if CONT = 0 and EXTEN = 10 then the ADSTART will be cleared when EOC flag is set.
Ed.