STM32H753 - LSE Drive Strength and GPIO Speed

[Manikandan]

Hi Team,

We are using the STM32H753 in our design.

For the signal quality, we are adjusting the LSE drive strength.

Below are the four options available in drive strength,

1. low drive
2. medium low drive
3. medium high drive
4. high drive

Kindly let us know drive current value of each options for understanding.

Also we want to know for the GPIOs as well,

1. Speed = GPIO_SPEED_FREQ_VERY_HIGH
2. Speed = GPIO_SPEED_FREQ_HIGH
3. Speed = GPIO_SPEED_FREQ_MEDIUM
4. Speed = GPIO_SPEED_FREQ_LOW

Kindly let us know drive current value of each options.

Thanks

Manikandan R

Thanks

Manikandan R

[mƎALLEm]

Hello,

Please kindly separate different questions on different threads.

Let's keep this thread for LSE drive level selection and open a new thread for GPIO IO speed.

Thank you for your understanding.

[mƎALLEm]

The only current parameter we give in the datasheet (for the silicon rev V) is the LSE current consumption on IDD based on the drive level:

[STOne-32]

Dear @Manikandan ,

LSE drive has nothing to do with signal integrity and here the LSE is 32,768KHz crystal frequency .  LSE drive is explained in here :https://www.st.com/resource/en/application_note/an2867-guidelines-for-oscillator-design-on-stm8afals-and-stm32-mcusmpus-stmicroelectronics.pdf

However, GPIO output drive is very key for signal integrity and use the right drive based on the External signal frequency and load as in datasheet - I/O dynamic speed characteristics.

Hope it helps,

STOne-32

[Tesla DeLorean]

Aren't such things touched on in the Data Sheet?

It's more of a SLEW RATE (OSPEED) setting, depends on the voltages and also "IO Compensation" settings. So more of a capacitive load thing vs resistive load.

The current per pin, and collectively a maximum for all pins, is addressed.