Stm32H723 Ethernet DMA tail pointer

[chris1seto]

Hi,

I understand this has been discussed before, but can we please get an official explanation of how the dma tail pointer works in the Stm32H7 eth mac ip block? It's extremely difficult to write software to support the eth mac when the docs and example drivers are questionable and the actual functioning of the silicon is simply left to guess by a lack of official information.

Issue: 2974/3357 RM0468 Rev 3 clearly says that the tail pointer is "an offset from the base", ie, it is not an absolute address or an index of a descriptor (from 0 to max descriptors). This completely disagrees with the cube driver which sets this as an absolute address: https://github.com/STMicroelectronics/stm32h7xx_hal_driver/blob/a7ac5eac41b0c73072401566237ba202f07251cf/Src/stm32h7xx_hal_eth.c#L1218

So, can we get an official no-further-questions answer for what kind of address is supposed to go in the tail pointer?

Thanks,

[chris1seto]

Hi @STea Thank you for conforming that.

I believe I may have found a bug in the HAL driver. Please see the following ticket: https://github.com/STMicroelectronics/stm32h7xx_hal_driver/issues/65

[STea]

Hello @chris1seto ,

I will proceed by closing this thread as it is actively discussed in your other thread.

Regards

[chris1seto]

Hey @LCE , I had another question.

How does DMA know how big each descriptor is? I noticed you added additional fields to the descriptor struct, and that the ST driver contains a few extra of its own. How does it know the length of those extra fields so it can index the descriptor list? I searched all through the driver looking for the size of the descriptor struct to be considered, but I couldn't find anything.

Thanks,

[LCE]

It's well hidden in ETH->DMACCR.

/* DMACCR: Channel control register
 *	DSL		= xxx: Descriptor Skip Length,
 *				-> depends on "extra data" in descriptor,
 *				for now 2x 32bit vars
 *	PBLX8	= 0: NOT 8x PBL
 * 	MSS[13:0]: Maximum Segment Size, only used when TSE set for
 *				packet segmenting in HW
 */
	u32TempReg = (uint32_t)TCP_MSS;

/* DSL depends on descriptor size */
	uint32_t u32Dsl = ETH_DESCR_ARR_SIZE - ETH_DESCR_BASE_ARR_SIZE;
	if( u32Dsl > 7 )
	{
		#if DEBUG_ETHNETIF
			uart_printf("# ERR: EthDmaInit() Descriptor Skip Length = %lu\n\r", u32Dsl);
		#endif 	/* DEBUG_ETHNETIF */
		u32Dsl = 0;
	}
	u32TempReg |= (uint32_t)(u32Dsl << ETH_DMACCR_DSL_Pos);
	ETH->DMACCR = u32TempReg;

with:
#define	ETH_DESCR_BASE_ARR_SIZE		4
#define	ETH_DESCR_ARR_SIZE		(uint32_t)(sizeof(DmaTxDescriptors[0]) / 4)

Could be more elegant concerning the defines, maybe was a takeover from my F7 driver, which has different ETH / MAC.

[chris1seto]

That's what I suspected, I see it now:

https://github.com/STMicroelectronics/stm32h7xx_hal_driver/blob/a7ac5eac41b0c73072401566237ba202f07251cf/Src/stm32h7xx_hal_eth.c#L384

I wasn't expecting it to be in bits, so I didn't catch it at first.