STM32H7 Run* mode before configuring PWR_CR3

[Terry Greeniaus]

We are using the STM32H745 in one of our projects. We are using "LDO supply" mode (configuration 1 in Fig. 22 from RM0399 v3). Section 7.4 of RM0399 describes the power-up sequence, including a Run* mode where application code starts executing but is not allowed to write to RAM until one of the supply configurations has been selected by writing the write-once byte in PWR_CR3. The manual notes that RAM writes in Run* mode are forbidden:

• Section 7.4.1:
  • 4. Once the oscillator is stable, the system is initialized: Flash memory and option bytes are loaded and the CPU starts in limited run mode (Run*).
  • 5. The software shall then initialize the system including supply configuration programming in PWR control register 3 (PWR_CR3). Once the supply configuration has been configured, the ACTVOSRDY bit in PWR control status register 1 (PWR_CSR1) shall be checked to guarantee valid voltage levels:
    • a) As long as ACTVOSRDY indicates that voltage levels are invalid, the system is in Run* mode, write accesses to the RAMs are not permitted and VOS shall not be changed.
    • b) Once ACTVOSRDY indicates that voltage levels are valid, the system is in normal Run mode, write accesses to RAMs are allowed and VOS can be changed.
• Fig. 23: "In Run* mode, write operations to RAM are not allowed."
• Fig. 24: "In Run* mode, write operations to RAM are not allowed."

There may be other references; it is difficult to search for "Run*" in my PDF viewer since it ignores the star in the search box.

In our project, I had not been taking any special measures to avoid writes to RAM before setting the supply configuration. Looking at the STM32CubeH7 sample code I see that no special care is taken there either; global variables are accessed, non-inlined functions appear to be called requiring stack frames, etc., all before HAL_PWREx_ConfigSupply() is called to finally select a supply configuration.

Is the RM just flat-out wrong on this regard? Or is there are subset of RAMs that are safe to access from the default supply configuration before writing to PWR_CR3? Maybe by "RAM" they mean external RAMs and not SRAMs? Or is both my code (which seems to have been working fine for over a year) and the STM32CubeH7 code wrong and we're both just lucky?

I just did the work of updating my code to configure PWR_CR3 before any RAM accesses occur (including before doing any pushes to the stack), but am wondering if that was really necessary at all and if perhaps the RM or example code could be updated for consistency with one another.

Thanks,

TG

[Terry Greeniaus]

Would anyone from ST able to comment on this?

[Terry Greeniaus]

Still hoping that someone from ST may be able to comment...

[waclawek.jan]

This is a primarily user-driven forum, with only casual ST presence. You may want to contact ST directly, through FAE or the web support form.

My reading of the RM is, that after switching VOS, RAMs are unreliable until the new setting settles. Spin in a trivial loop. I am not ST and I don't use H7.

JW​

[Terry Greeniaus]

Yes, I realize this is a community-driven forum, however it also seems to be the easiest place to get feedback from ST employees who have graciously updated documentation, replied to questions and fixed documentation errors in the past when I have posted here.

I don't follow your reading of the RM. This question is about accesses to RAM prior to any attempts to change VOS and specifically before the LDO/SMPS configuration is written in PWR_CR3. The manual says writes to RAM before setting the configuration are forbidden; Cube sample code performs reads and writes to RAM before setting PWR_CR3 (which is not set until after main() is invoked) - either a violation of the manual or the manual is wrong.

I have submitted an online support ticket and will update this thread when I get a response.

[waclawek.jan]

> get feedback from ST employees who have graciously updated documentation,

> replied to questions and fixed documentation errors

Yes, they do, occasionally. What I'm trying to say is, don't hold your breath.

> I don't follow your reading of the RM.

Yes, I am probably wrong. Is I've said, I don't use the H7, and obviously there's more to it than just what I've seen at a glimpse to RM. Sorry.

JW

[JBURB · Accepted solution]

Hello,

You could have a look at RM0468 rev3 (targeting STM32H72/73 but this short explanation can be adapted to STM32H74/75 ).

In " 6.4.1 System supply startup", you can find a chapter giving an example how to deal with RUN*, it can be adapted to LDO supply easily.

*******************************************

How to exit from Run* mode

As the Run* mode does not allow accessing RAM, PWR configuration must be done in the

startup file. Below an example of code for SMPS supply that can be adapted for any other

mode, with some assembler knowledge:

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

;;

;; Exit Run* mode to Direct SMPS mode

;;

THUMB

PUBWEAK ExitRun0ModeToDirectSMPSMode

SECTION .text:CODE:NOROOT:REORDER(1)

ExitRun0ModeToDirectSMPSMode

MOV R1, #0x4804

MOVT R1, #0x5802

LDR R0,[R1, #+8]

BIC R0,R0,#0x2

STR R0,[R1, #+8]

wait_actvosrdy:

LDR R2,[R1, #+0]

LSLS R0,R2,#+18

BPL.N wait_actvosrdy

BX LR

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

;;

;; Default interrupt handlers.

;;

THUMB

PUBWEAK Reset_Handler

SECTION .text:CODE:NOROOT:REORDER(2)

Reset_Handler

LDR R0, =ExitRun0ModeToDirectSMPSMode

BLX R0

LDR R0, =SystemInit

BLX R0

LDR R0, =__iar_program_start

BX R0

******************************************************

I hope it can help you.

Br,

Jacky

[Terry Greeniaus]

I had a discussion with the online support people about this. At first I received a response that conflicted with what @JBURB​ wrote.

The summary of the initial response was: "there is no risk on RAM content; RAM Content is preserved", and "There is no functional limitation in Run* mode, but it is recommended to set the PWR_CR3 as soon as possible to avoid RAM read/write operations with higher voltage than the target one during the Run* mode."

After pointing out Jacky's observation that other H7 Reference Manuals have this new section about how to exit from Run* mode, I received the following reply: "From the design team, I've learned they are planning to add the section you referenced in RM0468 rev 3 to the next revision of RM0399. The example code will also be evaluated to add the assembly code into the startup files."

So, it sounds like they MAY update the STM32Cube sample code to perform the PWR_CR3 switch in assembly before touching RAM. The recommendation seems to absolutely be to set PWR_CR3 before touching RAM, but on the other hand the reply that they MAY (or MAY NOT) update the sample code seems to imply that maybe it's still okay?

Anyways, I am happy that I made the initial choice to address this in my own code base and hopefully this discussion may be helpful to others trying to understand H7 and PWR_CR3.