STM32H7 controlling 1.5MSPS ADC with parallel interface

[juan luis ferrando]

Posted on February 05, 2018 at 10:19

Hi all,

I am trying to implement a measurement system using STM32H7 microcontroller. The ADC used will be LTC2320-14 from Linear Technology. I am trying to find what would be the right pheripherial to control and receive data from this ADC. In the past I have used STM32F4 to control high speed ADC by they were using serial interface so SPI pheriperial worked perfectly for this. However, in this new application since the ADC is simultaneous sampling, the output data must be read in parallel. It provides the data in 4 serial lines working in parallel. The clock signal must be generated by the  STM32H7 at a frequency of 100MHz to reach the 1.5MSPS rate that can be reachable with STM32H7. I though an option could be to use Quad-SPI interface deleting the command, address and mode bits but I do not know if this can be done.Maybe, also FMC pheripherial could be used. I would apreciate if you could suggest any solution for this.

Best regards,

Juan Luis

#multichannel-adc #stm32h7

[waclawek.jan]

Posted on February 05, 2018 at 10:29

Timer-triggered DMA from FMC to any other memory.

JW

[juan luis ferrando]

Posted on February 05, 2018 at 11:00

Thanks for your quick response!. Could you please provide a bit more information please? for example, what would be exactly the configuration of FMC? to configure the peripherials I use STMCubeMX. If you select the required microcontroller in the FMC settings I only see NORflash, PSRAM, SRAM , SDRAM , ROM, LCD. I do not know exactly what to select and what configuration to use.

The DMA transfer is more cleare to me since I have used it in the past. I have also seen you previous post which is very useful:

https://community.st.com/0D50X00009XkYz0SAF

The idea is to transmit the data from the ADC direct to an external SDRAM module. Do you think this would be straightforward or it is a complex and will take the STM32H7 to its limit? The maximum data speed would be 12 MBytes/sec since it is 2 bytes per sample, 4 channels, 1.5 MSPS. (2bytes*4channels*1.5MHz=12MBytes/sec)

Any guidance on this would be really apreciated.

Many thanks!

Best regards,

Juan Luis

[juan luis ferrando]

Posted on February 05, 2018 at 12:25

Do you suggest the diagram attached? Can the 4 SPI work in parallel??

Since there is a peripherial controller QSPI, could not be used for thisi application?

________________ Attachments : ADC SPI connection diagram.png : https://st--c.eu10.content.force.com/sfc/dist/version/download/?oid=00Db0000000YtG6&ids=0680X000006Hxoz&d=%2Fa%2F0X0000000b3T%2FfSKpkZvSVQ1M0tZN3DQeq8fBPACWQMv8aEAGk2X_FEU&asPdf=false

[waclawek.jan]

Posted on February 05, 2018 at 11:35

Ah, *that* sort of parallel... sorry, I just skimmed your first post and haven't had look at the ADC's DS.

In this particular case, I personally would perhaps go for using 4 SPI modules (the 'H7 should have 6 of them according to the DS), 1 master and 3 slaves, with clock connected externally. Deserializing parallel-captured data sounds like a real processor-time killer.

JW

[waclawek.jan]

Posted on February 05, 2018 at 12:47

Do you suggest the diagram attached?

Yes. It's upon you to work out the details with clocks timing etc., of course.

Can the 4 SPI work in parallel??

Can 4 shift registers (e.g. 74HC165) work in parallel, if their clocks are connected?

Since there is a peripherial controller QSPI, could not be used for thisi application?

I don't know, but even if it could be used, you'd have the problem with deserializing parallel-captured data again.

JW

[Evgeny Erlihman]

Posted on February 07, 2018 at 16:39

Have you considered using the internal ADCs? They can work with DMA and offload the processor.

[Joerg Wagner]

Posted on February 08, 2018 at 00:13

Take a look at the application note AN4666:

http://www.st.com/content/ccc/resource/technical/document/application_note/7a/88/df/e3/d3/36/40/29/DM00169730.pdf/files/DM00169730.pdf/jcr:content/translations/en.DM00169730.pdf