2023-06-16 12:30 PM
I'm attempting to bring up a project on a Nucleo-H755 board using only the CM4 core (the CM7's boot is disabled). I have proved out that the ADC works as expected with polling and interrupts, but I can't get DMAs to function.
I found and reviewed the H7 DMA issues knowledgebase issue, but I don't believe this is relevant as I am not using the CM7 core and I have confirmed that the DMA target buffer is in D2 SRAM. I have ensured that `MX_DMA_Init` is called before `MX_ADC_Init` as suggested elsewhere, and I have reviewed myriad examples for other STM32 parts, all of which match what I'm trying to do, with no success.
I've removed the M7/M4 interlock, as I'm only booting the M4, and I have moved the `SystemClock_Config` function from the CM7 main.c to the CM4.
I've attached both my main.c and .ioc file here, but the general flow of the program is:
uint32_t result = 0xFFFFFFFF;
uint32_t adc_buf[2];
void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc) {
result -= 1;
}
int main(void)
{
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
HAL_Init();
SystemClock_Config();
/* Initialize all configured peripherals */
MX_GPIO_Init();
MX_DMA_Init();
MX_ADC1_Init();
HAL_ADCEx_Calibration_Start(&hadc1, ADC_CALIB_OFFSET, LL_ADC_SINGLE_ENDED);
HAL_Delay(10);
while (1)
{
HAL_ADC_Start_DMA(&hadc1, adc_buf, 1);
HAL_Delay(1);
}
}
I never see `HAL_ADC_ConvCpltCallback` called, and the data in `adc_buf` never changes.
I'd appreciate any help - I imagine I'm missing something simple, but I've run out of ideas.
Solved! Go to Solution.
2023-06-22 08:55 AM
A coworker helped me suss out the missing setting: The "Conversion Data Management Mode" setting needs to be in one of the DMA modes - in this case, DMA One Shot Mode. This properly enables the triggers the interrupts.
2023-06-22 08:55 AM
A coworker helped me suss out the missing setting: The "Conversion Data Management Mode" setting needs to be in one of the DMA modes - in this case, DMA One Shot Mode. This properly enables the triggers the interrupts.