STM32G473 datasheet - upper limit on ADC external trigger period

[hepoun]

Hi,

maybe I don't know how/where to look, but I can't find any info why in datasheet for STM32G473 there is the max value for T_trig (external trigger period) in ADC timing characteristics (see the attached image). I several datasheets for several other families and there was maximal value for f_trig instead, which seems perfectly natural to me.

Could anyone point me in the right direction?

Thx

[Imen.D]

Hello @hepoun ,

There is no reason – probably some historical reason.

I will escalate your feedback to put there f_trig instead.

Thank you for your contribution.

[Imen.D]

Hi @hepoun ,

An internal ticket number 172935 is submitted in order to update the impacted STM32G4 Datasheets on this point.

(PS: Ticket number 172935 is an internal tracking number and is not accessible or usable by customers)

[Imen.D]

Hi @hepoun,

After deep check, here is the reason for T_trig instead of F_trig: 
In datasheet, we put there also minimum value for T_trig - to inform our customers about latency times.
Next point is that the minimum f_trig is already included in the ADC parameters - in parameter "fs - sampling time, continuous mode". The minimum value is set to 1kHz.

[waclawek.jan · Accepted solution]

I'd say it's related to this erratum:

(1ms rang a bell)

JW

[hepoun]

Hi @Imen.D ,

thank you for your answer.
What I understand from it is, that T_trig_max is derived from minimal value of f_s sampling rate in continuous mode.
I must admit that it still doesn't make much sense to me, AFAIK in continuous conversion mode an external trigger is needed just once, no repeating of the external trigger necessary, that would give us T_trig_max = +inf, wouldn't it?

Just a sidenote: I have no problem whatsoever with a minimum value for T_trig.

[hepoun]

Thank you JW,

this seems to be the answer I was looking for.

h.