STM32G0B1 FDCAN and bit timing

[Kraal]

Hi,

I would like to use the FDCAN peripheral of the STM32G0B1, for CAN2.0B.

Coming from the F0 CAN peripheral, I can understand most of the new peripheral easily.

However, for the bit timing, per FDCAN specification, there are 2 bit times: the nominal (like standard CAN) and the one for the fast data. So far so good.

For the nominal bit time, it is written at the bottom of the page 1232 of the RM0444 (36.4.7) that the CAN bit time may (not must ?) be programmed in the range of 4 to 81 time quanta.

My questions are:

• This limitation is strange as the bit time is made of [NTSEG1 + NTSEG2 + 3] * tq, with NTSEG1/2 being as high as 255, 127 respectiveley, so well above 81.
• What happens if the total of bit quanta is equal to 3 or above 81 ?
• This limitation is not mentionned in the data bit time register. Is it also applicable ?

Best regards.

[BEvan.2]

Hi Kraal,

Did you figure anything out regarding this issue. I'm confused by the limitation too and it seems it's only mentioned very briefly in that paragraph.

ST, can you please confirm or rephrase this. Is [NTSEG1 + NTSEG2 + 3] actually limited to a range of 4 to 81 tq?

Regards,

Ben

[Kraal]

Hi Ben,

Since I had no answer from ST, I went forward and kept the bit time within [4; 81] for both nominal and data bit times.

Since I am using CAN2.0B at a rate of 500kbps, it is not a problem.

@Imen DAHMEN​ Can we have an answer from ST regarding this documentation issue, please ?

Best regards,

Kraal

[Imen.D]

Hello @Kraal​ ,

Thank you for flagging this for me!

I will check this point and come back to you soon with update.

Thanks

Imen

[AAlex.20]

Bittime above 80tq simply doesn`t work, tried 80tq - ok, 100tq, 200tq - doesn` work(controller goes to bus off state)

[BEvan.2]

@Community member​ from the quick testing I performed, this was not the case for me. I could run my nominal bitrate with more than 80tq and it worked fine. This was classic CAN and not CAN FD though.

Additionally, I'm using an STM32H742 (rev V) chip which contains the same paragraph within the datasheet about the tq restriction but may explain why we're seeing different behaviour.

I'll perform some further testing over the weekend to see if there is a point where it stops working for me.

Cheers,

Ben

[BEvan.2]

Hi @Imen DAHMEN​ 

Did you end up finding an answer to this?

I'm using an STM32H742 (rev V) chip and the statement does not seem true for this chip. It seems I can successfully run with an NTSEG1 + NTSEG2 far over 81 without issue.

Kind Regards,

Ben

[BEvan.2]

@Imen.D may you please follow this up. I'd still like to get an official answer on this and would like to know if the datasheet is incorrect.

Thanks,

Ben