STM32G031F8 Documentation Error on NVIC Priority Register addresses?

[JCase.1]

I am coding an STM32G031F8P6. I want to set some interrupt priority values. I am looking at the programming manual, PM0223. In section 4.2 (page 82) Table 25 says that the priority registers NVIC_IPR0-7 are 0xE000E400-0xE000E4EF. That doesn't make sense, as it implies a block 240 bytes long. This block should be 32 bytes long. There is no updated version of this document, nor is there an errata listing for this. Are the priority registers the first 8 words (32 bytes) in this block, or evenly distributed in the 240 byte block?

[waclawek.jan]

From the horse's mouth:

 

But ST is actually innocent here, as PMs are only slightly customized versions of ARM's own "Generic User Guide", and that contains the same error, https://developer.arm.com/documentation/dui0662/b/Cortex-M0--Peripherals/Nested-Vectored-Interrupt-Controller?lang=en

JW

[JCase.1]

Thank you Jan. Not unexpected, but good to see it properly documented.

[KDJEM.1]

Hello @JCase.1​,

Thanks for reporting the issue.

You're right, the NVIC_IPR0-7 addresses are 0xE000E400- 0xE000E41C.

I confirm this issue and I reported internally.

Internal ticket number: 139461 (This is an internal tracking number and is not accessible or usable by customers).

Kaouthar

[waclawek.jan]

Thanks, Kaouthar.

Jan

[Piranha]

By the way... Is it just me or ARM is actually even more reluctant to fix the documentation than ST?

Except for Cortex-M0, the description of LDM/STM instructions is wrong for all Cortex-M cores, including the new Cortex-M33.

https://stackoverflow.com/questions/55153838/confusion-about-ldmdb-in-arm-assembly

For example:

https://developer.arm.com/documentation/dui0646/c/The-Cortex-M7-Instruction-Set/Memory-access-instructions/LDM-and-STM

And, of course, all of the respective ST's CPU programming manuals are also wrong regarding this.

[KDJEM.1 · Accepted solution]

Hello @JCase.1​ ,

This typo is fixed in PM0223 Rev 6.

Thank you.

Kaouthar