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LCE
LCE
Principal II
August 3, 2022
Solved

STM32F767 SAI SPDIF Output, NODIV and Clock Generator

  • August 3, 2022
  • 5 replies
  • 1314 views

STM32F767 SAI SPDIF Output, NODIV and Clock Generator

When NODIV bit is set in SAIx->CR1, the SPDIF output frequency is as it should be.

Example:

clock in is 25.6 MHz, sampling rate is 200 kHz, factor is 128, as it should with "symbol rate" (2 channels with 32 bit -> 64) times 2 (biphase mark code).

But when the NODIV bit is cleared (MCLK divider is ON), and MCKDIV[3:0] is set to 0000, the clock is divided by 4. (clock in 25M6 -> sampling rate 50k)

Why's that so?

And why is that not documented? (RM0410, latest)

Or what am I mssing?

Thanks in advance.

This topic has been closed for replies.
Best answer by KDJEM.1

Hi @Community member​ ,

Thanks for bringing this issue to our attention.

I confirm the issue.

The correct system formula is:

  • When NODIV = 1, then Master clock divider, and bit-clock divider are bypassed. So, if the kernel clock input 25.6 MHz, the sampling rate is 25.6 M/128 = 200 kHz.
  • When NODIV = 0, and Master clock divider=0, the bit-clock divider is doing a division by 4. So, the bit clock provided to SPDIF block is the SAI kernel clock divided by 4.

I reported this issue internally.

Internal ticket number: 136378 (This is an internal tracking number and is not accessible or usable by customers).

When your question is answered, please close this topic by choosing Select as Best. This will help other users find that answer faster.

Thank you

Kouthar

5 replies

waclawek.jan
waclawek.jan
Super User
August 3, 2022

I don't have answers, just want to point out that the SAI documentation is generally lacking precision and details.

https://community.st.com/s/question/0D50X00009XkaBlSAJ/f446-documentation-sai-clock-generator

JW

LCE
LCEAuthor
Principal II
August 4, 2022

Thanks Jan!

Maybe some ST pro can say something about that?

It would be nice to know if I got something wrong or the documentation.

waclawek.jan
waclawek.jan
Super User
August 4, 2022

ST pros rarely come here (note the date of that post of mine and the number of replies from ST pros there). You may want to submit this to ST as a request for support through the web support form.

JW

LCE
LCEAuthor
Principal II
August 4, 2022

Thanks, I'l try that.

KDJEM.1
KDJEM.1Best answer
ST Technical Moderator
October 10, 2022

Hi @Community member​ ,

Thanks for bringing this issue to our attention.

I confirm the issue.

The correct system formula is:

  • When NODIV = 1, then Master clock divider, and bit-clock divider are bypassed. So, if the kernel clock input 25.6 MHz, the sampling rate is 25.6 M/128 = 200 kHz.
  • When NODIV = 0, and Master clock divider=0, the bit-clock divider is doing a division by 4. So, the bit clock provided to SPDIF block is the SAI kernel clock divided by 4.

I reported this issue internally.

Internal ticket number: 136378 (This is an internal tracking number and is not accessible or usable by customers).

When your question is answered, please close this topic by choosing Select as Best. This will help other users find that answer faster.

Thank you

Kouthar

To give better visibility on the answered topics, please click on "Best answer" on the reply which solved your issue or answered your question.
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