STM32F7 Memory map in AN4839

[Nevyn]

We have a question about the memory map in section 3.1 of AN4839. The note states that "by default the MPU is disabled and that in this case the memory map is defined as the default address map".

Immediately under this statement is a table with a memory map. Is this the default memory map ? I am reading this as a default table that can be changed but another developer is reading this as requirements on the memory regions.

We have a QSPI flash mapped at 0x90000000 and I need this to be strongly ordered which according to AN4839 means that this needs to be sharable. We are getting odd behaviour due to speculative reads, hence the need for strongly ordered memory.

Regards,

Mark

[KDJEM.1 · Accepted solution]

Hello @Nevyn​,

When using an STM32 product based on a Cortex®-M7 (such as STM32F7 Series and STM32H7 Series), it is highly recommended to configure the QUADSPI memory region accessible in Memory-mapped mode as strongly ordered memory. For that, it is necessary to change memory attributes from normal to a strongly ordered or to device memory thanks to the MPU.

To do that, please refer to AN4838 and precisely MPU setting example with STM32Cube HAL on Armv6 and Armv7 architectures section and Cortex-M7 constraint speculative prefetch section.

Also I advise you to take a look at this video.

When your question is answered, please close this topic by choosing Select as Best. This will help other users find that answer faster.

Thank you

Kaouthar

[Piranha]

Or, instead of just dumbly disabling everything and loosing performance, learn how to actually deal with the memory:

https://community.st.com/s/question/0D50X0000C4Nk4GSQS/bug-missing-compiler-and-cpu-memory-barriers

https://community.st.com/s/question/0D53W00001Z9K9TSAV/maintaining-cpu-data-cache-coherence-for-dma-buffers