STM32F746G-DISCO External SDRAM Code Execution Problem

[THoll.4]

Hello everyone,

I’ve been working on a project using the STM32F7 Discovery board and I’m trying to execute code from external SDRAM. However, I’ve run into a puzzling issue and could use some guidance. Here’s a detailed breakdown of the problem:

Setup:

• I’ve successfully configured the FMC to interface with external SDRAM.
• I’ve also set up the MPU to enable execution from the SDRAM region.
• The SDRAM initialization sequence follows the recommended steps (clock enable, precharge, auto-refresh, and load mode register).
• I’ve disabled MPU caching to rule out cache-related issues for now.

The Problem:

• When I attempt to jump to code that’s loaded in SDRAM, the program counter (PC) seems to advance and execute instructions, but none of the registers (R0-R15) are being updated as expected.

• There are no hard faults or other exceptions being triggered, which is unusual because, in other attempts with incorrect MPU settings, I’ve triggered hard faults for unexecutable regions.

• It appears as if the CPU is fetching instructions from SDRAM, but they have no effect on the processor state.

What I’ve Tried:

1. MPU Configuration:

   • I’ve ensured the SDRAM region is marked as executable with the correct access permissions:

     MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_ENABLE;

   • I’ve experimented with marking the region as shareable and non-shareable, but enabling shareable seemed to cause other issues with synchronization, so I left it as non-shareable.

2. Cache Settings:

   • I tried disabling the instruction cache and invalidating the cache before execution, using:

     SCB_InvalidateICache(); SCB_DisableICache();

   • This did not resolve the issue, and the behavior remains the same.

3. Thumb Mode:

   • I made sure the jump address to the SDRAM code has the least significant bit (LSB) set to 1 to ensure the processor switches to Thumb mode:

4. FMC/SDRAM Timing:

   • I’ve double-checked the SDRAM timing parameters like CAS latency, row cycle delay, write recovery time, etc., and they seem to match the SDRAM chip’s datasheet.

5. Fault Handlers:

   • I’ve set up fault handlers (Hard Fault, Memory Management, Bus Fault), but none of them are getting triggered during execution.

6. Basic Memory Test:

   • I ran simple memory tests to write and read data from the SDRAM, and it functions as expected for data storage. The issue only arises when trying to execute code from the SDRAM.

Observations:

• The CPU seems to fetch instructions from SDRAM (since the PC advances), but these instructions don’t affect the registers.

• No hard faults or other exceptions occur, which would typically happen if the region wasn’t properly executable.

Questions:

1. What could cause the CPU to "silently" fail to execute instructions from SDRAM without triggering a hard fault?

2. Could this be related to specific instruction set issues (Thumb/ARM) or some subtle MPU or FMC timing misconfiguration?

3. Has anyone experienced similar issues running code from external SDRAM on the STM32F7?

Any insights or suggestions would be greatly appreciated!

[SofLit]

Hello,

Try to inspire from one of the examples provided in X-CUBE-32F7PERF:

– “7-ExtSDRAM-Swapped_rwDTCM”
– "7-ExtPSRAM_rwDTCM"

Linked to the application note AN4667 "STM32F7 Series system architecture and performance".