STM32F466RE: How many clock cycles to access data sram memory?
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‎2024-10-04 11:37 AM
For application benchmarking, I would like to access the data memory of the STM32F466RE in a single cycle.
What is the data load latency of the STM32F466RE from data SRAM at 84MHz?
and, if it is not single cycle, can I reduce the core frequency to decrease the number of SRAM access cycles?
Thank you.
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RCC
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STM32F4 Series
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‎2024-10-04 12:56 PM
see ds:
If you feel a post has answered your question, please click "Accept as Solution".
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‎2024-10-04 12:56 PM
see ds:
If you feel a post has answered your question, please click "Accept as Solution".
