STM32F466RE: How many clock cycles to access data sram memory?

[kag_embedded]

For application benchmarking, I would like to access the data memory of the STM32F466RE in a single cycle.
What is the data load latency of the STM32F466RE from data SRAM at 84MHz?

and, if it is not single cycle, can I reduce the core frequency to decrease the number of SRAM access cycles?

Thank you.

[AScha.3 · Accepted solution]

see ds: