STM32 PLL clock source doesn't work

[mike louaillier]

Posted on June 18, 2017 at 09:21

Hello i have a program on the 32F030f4p6 chip for testing the system clock frequency. It blinks an LED at about 1Hz. the problem is that when i change the PLL multiplier from 2 to 12 the LED still blinks at the same 1Hz. i configured the system clock for 48MHz but it seems to be running at 8MHz. i don't know what i'm doing wrong.

#include 'stm32f030x4.h'
int main(void)
{
// sysclock configuration
 RCC->CR |= RCC_CR_HSION; // 8MHz
 RCC->CR |= RCC_CR_PLLON; 
 RCC->CFGR &= ~RCC_CFGR_PLLSRC;
 RCC->CFGR |= RCC_CFGR_PLLSRC_HSI_DIV2; // PLL source = 4MHz
 RCC->CFGR &= ~RCC_CFGR_PLLMUL;
 RCC->CFGR |= RCC_CFGR_PLLMUL12; // <-- changing the multiplier has no effect on LED frequency
 RCC->CFGR &= ~RCC_CFGR_SW;
 RCC->CFGR |= RCC_CFGR_SW_PLL; // PLL selected as system clock
 RCC->CFGR &= ~RCC_CFGR_HPRE;
 RCC->CFGR |= RCC_CFGR_HPRE_DIV1; // ahbclk not divided
 RCC->CFGR &= ~RCC_CFGR_PPRE;
 RCC->CFGR &= RCC_CFGR_PPRE_DIV1; // apbclk not divided
 RCC->AHBENR |= RCC_AHBENR_GPIOAEN;
// GPIO pin configuration
 pinpos = 4;
 GPIOA->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEEDR0 << (pinpos * 2));
 GPIOA->OSPEEDR |= ((uint32_t)(0x03) << (pinpos * 2)); // high speed 50MHz
 GPIOA->OTYPER &= ~((GPIO_OTYPER_OT_0) << ((uint16_t)pinpos));
 GPIOA->OTYPER |= (uint16_t)(((uint16_t)0x00) << ((uint16_t)pinpos)); // type push/pull
 GPIOA->MODER &= ~(GPIO_MODER_MODER0 << (pinpos * 2));
 GPIOA->MODER |= (((uint32_t)0x01) << (pinpos * 2)); // mode = output
 GPIOA->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << ((uint16_t)pinpos * 2));
 GPIOA->PUPDR |= (((uint32_t)0x00) << (pinpos * 2)); // no pull up or down
 while(1){
 GPIOA->ODR ^= (1 << 4); // toggle LED
 for (y = 0; y<500; y++){ // delay about 1 second
 for (x = 0; x<500; x++){}
 }
 }
}

#stm-32f030f4p6-pll-configuration

[waclawek.jan · Accepted solution]

Posted on June 18, 2017 at 11:13

You cannot switch PLL multiplier while PLL is on, and you have to wait until PLL locks after switching it on, before using as a system clock.

See the PLL configuration modification code example in appendix A in RM.

Also note, that FLASH latency has to be set properly prior switching to a higher system clock, if running from FLASH.

JW

[mike louaillier]

Posted on June 18, 2017 at 23:53

much obliged now i got it goin on :)

[Khouloud GARSI]

Posted on June 19, 2017 at 13:40

Hi Mike,

Happy that your issue is solved .

Could you please mark the question as answered. This will help to m

inimize the duplication of subjects treating issues already solved.

https://community.st.com/0D50X00009bMM5DSAW

 

Khouloud.

[YAkse]

Your note about FLASH latency... Saved my day. I was about to go crazy. Thanks.