SPI data size reducuction to 1-bit

[JSext.1]

I have a rather strange request, but I am communicating to a Digital Potentiometer (AD5227) over SPI.  The chip has 64 available positions, but can only increment or decremement its position by 1 for each clock cycle.  To increment by 1, a 1 is placed on the MOSI, and to decrement a 0.  The issue is that to increment by 1 over SPI (8-bit) I have to send, 10101011, which is inefficient.  I hoped I could change this to 1-bit, but I am limited to a minimum option of 4-bits in STMCubeIDE.  Is it possible to change this to 1-bit?  I also then need to change it back to 8-bits for the other devices on the SPI.  I am unfortuantely limited by the number of pins available on the MCU otherwise I would use 3 more dedicated pins to communicate to this chip.  Thanks for your help   

[TDK]

No, the lowest word size for the SPI on the F7 is 4 bits. CubeMX is enforcing a hardware limitation.

[JSext.1]

Thanks for the quick reply.  I was hopful there would be a solution, but nevermind.  I think I will search for an alternative chip. 

[Bob S]

When you need to change the digital pot you could disable the SPI via __HAL_SPI_DISABLE(handle), reconfigure the SCLK, MOSI and chip select pins as normal outputs, bit-bang your 1-bit data, reconfigure the pins as special function pins and re-enable the SPI (via __HAL_SPI_ENABLE()).

Sounds like a lot, but not really that much.  Changing the GPIO config just requires writing to the MODER register.

[Pavel A.]

>  to increment by 1 over SPI (8-bit) I have to send, 10101011

This increments by two. You cannot increment or decrement by 1 bit with 8-bit or 4 bit SPI frames. Inefficient, because this chip is not really a SPI device.

[Peter BENSCH]

Indeed, it is somewhat cumbersome to operate such 1-bit interfaces with SPI. Nevertheless, it should still be feasible if you set an odd number of bits instead of an even number of bits for single steps. By the way, this is why your sequence 10101011 will increase the pot by two steps instead of one, because in this case the first 6 bits cancel out and only the last two bits are effective. Instead, you could set the SPI port to 5 bits and achieve the desired result with 1010x and x=setpoint.

For two or an even number of steps to be set simultaneously, the SPI would then be set to an even number of bits.

[TDK]

Bit-banging this interface seems straightforward. Why shoehorn SPI where it doesn't fit? Set U/D, then toggle CLK twice. Easy. CLK is max 50 MHz. You're not going to toggle GPIOs that fast.

[Andrei Chichak]

Yes, just set the up/down level on "MOSI", select the chip, and send out a HAL_GPIO_WritePin SET RESET on CLK and be done. The 10ns minimum is way slower than what you'll be able to generate. 

[waclawek.jan]

> CLK is max 50 MHz. You're not going to toggle GPIOs that fast.

On a 'F4, tight consecutive writes can toggle a GPIO pin once every system cycle. I'm convinced this is possible on 'F7, too.

JW

[AScha.3]

@waclawek.jan ,  @TDK  , just for info .... i tried pin toggle on H733 , because no clear data avail.

just at 200MHz core, but not so important here, because gpios on AHB4 bus, far away from core ! and max. is speed of this bus.

the "program" :

  while (1)
  {
	 // HAL_GPIO_WritePin(GPIOA, GPIO_PIN_2, GPIO_PIN_RESET);
	  GPIOA->BSRR = GPIO_PIN_2<<16;
	//  HAL_GPIO_WritePin(GPIOA, GPIO_PIN_2, GPIO_PIN_SET);
	  GPIOA->BSRR = GPIO_PIN_2;
  }

i got:  (check with DSO on pin )

speed test: @200MHz core
caches off, -O2 , HAL_GPIO_WritePin(): 250ns , hi-lo-loop 500ns
caches on, -O2 , HAL_GPIO_WritePin(): 40ns , hi-lo-loop 120ns
caches on, -O2 , GPIOA->BSRR = GPIO_PIN_2<<16;: 30ns , hi-lo-loop 60ns

compared to F4 core, F303 :

test speed: 15ns BSRR , mit while-loop 65ns (ohne Optim. 112ns / 260ns ) @60MHz core !

so: H7 can toggle in 30ns (at 200MHz core) , F4 in 15ns (at 60MHz core) !