Simultaneous ADC Readings from 15 SPI slaves

[BG1]

Hi ;

I need to know if it is possible to get 15 ADC samples from 15 ADC conversion ICs over SPI protocol with a single conversion trigger. My MCU has only 6 SPI peripherals and 3 of them have 16bits data size and the other 3 SPI have 32bits spi data size. Chip select is not a chance since I need to get these results simultaneously because interrupting the main timer interrupt routine over and over again will cause an overflow. Question is basically as is how to manage 6 SPI peripheral to fetch 15 ADC results in 12 bits under 1us , or maybe an extra IC related solution exists . My MCU is STM32H723Z.

[waclawek.jan]

There are many SPI-interfaced ADCs out there, some may support separate conversion-start and separate SPI-chip-select pins; others may support chaining (i.e. data-in data-out). Make a search.

JW

[Andrew Neil]

By definition, only one slave can be active on an SPI bus at any one time.

Therefore you would need 15 SPI buses to access 15 slaves truly simultaneously.

This is in the nature of SPI - nothing specific to STM32.

The first question must be, do they really need to be simultaneous?

If it really has to be simultaneous, As @Community member​ suggests, look for chips that can be triggered independently of reading.

Or chips that can perform multiple conversions in parallel.

Perhaps sample-and-hold in the analogue domain ... ?

[BG1]

Since it is multiphase control system , I need to sample all the feedback parameters at the same time. Parallel output ADCs connected to a GPIO [0 -15] that we can read only the IDR register can be a faster solution with only chip selecting of one of the 15 ADC ICs one at a time ? Is it a faster solution than SPI ? besides SPI high speed layout based issues maybe avoided by this way ? What I mean parallel by using a 12bits or 14bits parallel output ADC reflecting the result with its 12 or 14 data output IOs in parallel and paralleling every IO individiually.

[Andrew Neil]

@BG​ "I need to sample all the feedback parameters at the same time"

No, they don't need to be at the exact same time - just "close enough" that the error is negligible.

"Parallel output ADCs connected to a GPIO [0 -15] that we can read only the IDR register can be a faster solution with only chip selecting of one of the 15 ADC ICs one at a time ?"

So that's still not reading at the exact same time - is it?

Yes, in general, parallel interfaces are faster than serial - because you get everything at once, instead of just one bit at a time.

But what you can actually achieve in practice is another question.

SPI can go pretty fast - have you done the sums to see if it's "fast enough"?

[S.Ma]

Do you need 1MHz continuous dampling rate?

Let us assume all adc can receive the same trigger signal to convert at the same time, each adc is 12 clocks, 6 spi with 3 adc each is 36 mhz spi clock rate plus margins. As long as all adc are not 1meter away, should be ok. Now, assuming all spi can be dma assisted and you use say 6x6 bit mode, you endup with 6x6 bytes buffer to process in 1 usec and manage the parasitic interrupts. Will the core have enough time to process the data with spare time for the rest?

Maybe find a special multichannel adc as you are trying to make a 15 channels oscilloscope....