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Set PLL as the system clock for STM32F401RE board

DJ1
Associate III

Here i am trying to set PLL as the system clock using HSI of 16MHz for STM32F401RE development board, but the moment i enable the "SET PLL as system clock" bit, the system gets reset. What can be the reason for this. I am trying to achieve 70 MHz of frequency. 

Below is the code for the same.

 

 

int main()
{
// Clear the default 192 setting
RCC->PLLCFGR &= ~(192 << 6);
// Set 200 to PLLN
RCC->PLLCFGR |= (216 << 6);
// Clear the default 16 setting
RCC->PLLCFGR &= ~(16 << 0);
// Set 8 to PLLM
RCC->PLLCFGR |= (8 << 0);
// Set PLLP to 6
RCC->PLLCFGR |= (2 << 16);
 
// Turn on PLL from RCC CR Register
RCC->CR |= (1 << 24);
// SET PLL as system clock
RCC->CFGR |= (2 << 0);
// Wait while the status flag is set
while(!(RCC->CFGR >> 2 & 2));
 
 
while(1)
{
 
}
}
12 REPLIES 12
RhSilicon
Lead

I use the IDE to generate these types of codes automatically.

STM32_Clock_Cfg.png

I don't know if it can help in your case, but I found these videos about advanced debugging:

STM32CubeIDE Advanced Debug Features
https://youtube.com/playlist?list=PLnMKNibPkDnEDEsV7IBXNvg7oNn3MfRd6

 

There are also videos about the IDE:

https://www.youtube.com/@stmicroelectronics/search?query=STM32CubeIDE

 

There is a video search box in the profile:

YouTube_find.png

Danish1
Lead II

After turning on PLL with (note RCC_CR_PLLON is easier to read than 1<<24)

RCC->CR |= RCC_CR_PLLON;

you need to wait for the PLL to lock and show it is ready

while ((RCC->CR & RCC_CR_PLLRDY) == 0)
{ ; }

before changing clock mode. The time to lock is only something like 300us, but that's an eternity to a microcontroller.

TDK
Guru

Are you setting wait states appropriately before increasing the system clock?

If you feel a post has answered your question, please click "Accept as Solution".
DJ1
Associate III

Thanks for reply, I tried that as well, waiting until PLL is ready then only switching the system clock from HSI to PLL but still my code is jumping to infinite loop or sometimes giving error of address not found. Is this the correct of setting PLL clock?

ONadr.1
Senior III

Nucleo boards do not have the embedded crystal and capacitors for the MCU. The MCO from the integrated debugger is used as the HSI. For use with a crystal, it is necessary to first solder it, including auxiliary capacitors, and disconnect the clock supply from the debugger by desoldering the jumper.

DJ1
Associate III

True but i am using HSI, internal 16MHz frequency not the HSE

DJ1
Associate III

I have kept while loop until the HSIRDY and PLLRDY bits are SET to 1. Even after that the moment i run my code in debug mode, it comes out of debugging.

FBL
ST Employee

Hello @DJ1,

Have you tried using CubeMX? By default, using Nucleo-F401RE SYSCLK is configured to reach 84MHz.

To give better visibility on the answered topics, please click on Accept as Solution on the reply which solved your issue or answered your question.

Oh, sorry. Stupid oversight.