Hi!
In this MCU pin 1 is RTC_OUT1. Originally I didn't consider the RTC_OUT pin, so that there's not connection over it; however, I'm getting it through a wire. It must not affect the output frequency because it's supposed that the crystal circuitry is isolated from the pin.
Board is two layers with a massive ground planes in both of them as can be seen.
Thank you for led me towards the errata sheet, I found two possible sources for the misbehavior, but I haven't tried the workaround (it's only one; the second possible source of error has no solution):
2.2.1 Unstable LSI when it clocks RTC or CSS on LSE
Description
The LSI clock can become unstable (duty cycle different from 50 %) and its maximum frequency can become
significantly higher than 32 kHz, when:
• LSI clocks the RTC, or it clocks the clock security system (CSS) on LSE (which holds when the
LSECSSON bit set), and
• the VDD power domain is reset while the backup domain is not reset, which happens:
– upon exiting Shutdown mode
– if VBAT is separate from VDD and VDD goes off then on
– if VBAT is tied to VDD (internally in the package for products not featuring the VBAT pin, or externally)
and a short (< 1 ms) VDD drop under VDD(min) occurs
Workaround
Apply one of the following measures:
• Clock the RTC with LSE or HSE/32, without using the CSS on LSE
• If LSI clocks the RTC or when the LSECSSON bit is set, reset the backup domain upon each VDD power
up (when the PWRRSTF flag is set). If VBAT is separate from VDD, also restore the RTC configuration,
backup registers and anti-tampering configuration.
...
2.2.7 PC13 signal transitions disturb LSE
Description
The PC13 port toggling disturbs the LSE clock.
Workaround
None.
I can't use the RTC_OUT2 alternate pin because it's used for a critical part of my system and besides that, the PCB must be redesign (it's going to be easier to add a pull-down resistor on pin 1 instead of altering the whole design).
I'll keep you post ASAP I try the workaround. Greetings!
