{RESOLVED] STM32F0, why my PLL makes trouble?

[Pavel A.]

STM32F070RB stepping Y, with a 24MHz crystal as HSE. No LSE.

In the Cube, enabled PLL sourced from the HSE; SYSCLK goes to 48 MHz.

Then, as soon as I run thru HAL_RCC_OscConfig, debugger loses connection and I don't know what the chip does.

So I've switched the sysclk mux to HSE without PLL (24 Mhz), and then whole SystemClock_Config() passes well and everything looks good.

So I thought, 48 MHz is too much for this board. Enabled PLL again, with pre-div 1/2, to get the same 24 MHz. It fails again.

What can be the problem with the PLL? The board runs well at 24 MHz from the HSE, so the oscillator is good?

[AScha.3]

i would try : setting the pll in to 8 MHz (i have it here on F072 ), no problem on > 100 boards.

+ your VDDA is clean , with caps close to chip?

[gbm]

Before you set HCLK above 24 MHz, you must set Flash wait states to 1 in FLASH->ACR register. Enabling the prefetch buffer is also recommended.

[Pavel A.]

@gbm​ then how you explain that it fails with PLL at 24 mhz but runs fine on 24 mhz HSE?

[gbm · Accepted solution]

Maybe the 24 MHz oscillator is not reliable, and F070 it quite dumb here - it (officially) has no clock monitor. Personally, I would recommend to use 8 or 12 MHz crystal with F0; this would work even with incorrectly matched capacitors.

[waclawek.jan]

Single-step inside HAL_RCC_OscConfig() in disasm. Observe, which register is written by what value, and at which register write does the failure occur.

JW

[Pavel A.]

Thank you for all replies, guys. Replaced the board, the PLL problem went away.

It seems to be a bad board or maybe connectors, cables etc.