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STM32U585 LPTIM+SPI+LPDMA. Noise to SPI3_SCK causes fatal bit shifts in the bitstream

Associate II

During transmission and reception using STM32U585 LPTIM+SPI+LPDMA, noise to SPI3_SCK causes a fatal bit shift in the bitstream.



The condition on the left is normal and the oscilloscope waveform can be received exactly as expected.
However, if you introduce noise that shorts the SPI3_SCK terminal to ground, the state shown on the right will occur and the bits will continue to be received with a shift (11 bits in this example. It will change each time you try). There is no problem with the transmitting system, and only the receiving bits are shifted.

If this mode occurs, execute HAL_SPI_Abort(&hspi3).
Next, I found that restarting “HAL_SPI_TransmitReceive_DMA(&hspi3, (uint8_t*)aSpiTxBuffer, (uint8_t*)aSpiRxBuffer, (RXBUFFSIZE)” fixed it.

However, the problem is that I can't find any error-like behavior in any of the SPI3 or LPDMA instance values. It is very difficult to predict when to restart from a bit-shifted data string. Do you have any good ideas?


This system uses STM32U5 as the master and sends and receives data to and from slave devices. LPTIM3 operates in PWM mode and is used as a chip select for the slave device, as well as two LPDMA requests. LPDMA is in circular mode and performs SPI transmission and reception. It operates autonomously.






I have confirmed that the bit shift can be resolved by using LPDMA in linear mode instead of circular mode and restarting the LPDMA after each SPI transmission/reception.

However, LPTIM operates every 80usec (12.5kHz) and interrupt processing is heavy in linear mode. Furthermore, I am thinking of moving to LPBAM in the future, so I would like to use circular mode.
However, I am having trouble figuring out the conditions for determining when a bit shift phenomenon occurs in SPI reception due to unexpected external noise to SPI3_SCK.

Associate II

LPTIM3_CH1 is the trigger for LPDMA1_CH0. Start SPI3_TX








Associate II

The slave device connected to the master STM32 is a general-purpose A/D converter connected via SPI. Therefore, it was not possible to detect bit shift phenomena using the STM32 SPI's CRC function or NSS frame error function.

Operation at the moment of short circuit


The moment SPI3_SCK is shorted, the interval changes from 4ms to 7.2msec. Read the CBR1 value in the interrupt handler and stop at the breakpoint.
7.2msec (varies approximately between 6~18msec)

In HAL_SPI_TxRxCpltCallback callback function
  check_SPI_TX_cbr1 = handle_LPDMA1_Channel0.Instance->CBR1;
  check_SPI_RX_cbr1 = handle_LPDMA1_Channel1.Instance->CBR1;

SPI_TX_CBR1 124 (256-124=132)
SPI_RX_CBR1 253 (256-253=3)

Setting for interrupt when 256 byte transfer is completed.
・SPI3_TX has a record of 132 bytes transferred.
・SPI3_RX has a record of 3 bytes transferred.

I don't understand why the interrupt handler fires even though the CBR1 value is random (expected CBR1 value is 256)