Question abut stm32u5 internal flash

zqizh.1 · ‎2021-11-25

Hi,

The stm32u5's internal flash has feature "10 kcycles endurance on all Flash memory. 100 kcycles on 256 Kbytes per bank".

Please advise the memory address of "100 kcycles on 256 Kbytes per bank".

Thanks,

QiZhang

Amel NASRI · ‎2021-12-09

Hi @zqizh.1 ,

If you are looking for the flash memory addresses, you will find the anser in the reference manual RM0456 (precisely refer to the table "Flash module 2-Mbyte dual bank organization").

If your request is different from this, please precise what you are looking for.

-Amel

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Max · ‎2021-12-09

from RM0456:

zqizh.1 · ‎2021-12-09

Hi,

I am looking for the flash memory addresses of the specific 256 Kbytes which can be written and erased 100 000 times.

Please list down it here, or guide me to the page of the reference manual RM0456.

Thanks,

QiZhang

zqizh.1 · ‎2021-12-12

Hi,

I am looking for the flash memory addresses of the specific 256 Kbytes which can be written and erased 100 000 times.

Please list down it here, or guide me to the page of the reference manual RM0456.

Thanks,

QiZhang

Max · ‎2021-12-13

The answer is in the short text above.

There is no dedicated address for these 256k.

You can choose the location you want but you have to make sure the size of the area you cycle more than 10 000 times is 256k or less.

zqizh.1 · ‎2021-12-13

Hi,

According to my understanding, the NOR FLASH one cycle is erase-program on every page. the page size is 8K bytes,

During the flash operation, I can't find any limitation about 256KB,so don't know how the identify the two life cycle memory.

Please share more information and sample code about it.

Thanks,

QiZhang

Max · ‎2021-12-14

up to 32 pages (= 256kB) can be erased up to 100k times.

You choose the pages you want.

You must make sure that 32 pages maximum are cycled 10k times or more

LBöhm.1 · ‎2022-04-05

But how does this work? Is there a kind of wear leveling behind?

OliM · ‎2023-04-03

I am still flabbergasted by this. Technically this means you need internal wear leveling, rearranging (and identifying) those special 32 pages per bank while still maintaining near zero access latency. Or is there some magic reason why a NOR bank should hold up better if you just erase and rewrite a few pages of it?

Since this implies there is a write count per page: Is it possible to read out the value?