Dear All,
I am trying to develop a code for STM32H742VGT revision V. ADC1 and ADC2 work in regular simultaneous mode and they are set to convert 6 channels. All the settings are exactly same to have same sampling and conversion time. Of course, ADC1 and ADC2 convert different channels. DMA2 Stream 0 is dedicated to read conversion results from ADC12_Common Data register and write to RAM space when D-cache is disabled.
ADC1 Ranks are : Ch3, Ch7, C4, Ch17, Ch15, Ch19
ADC2 Ranks are : Ch8, Ch9, C5, Ch14, Ch18, Ch18
HAL_DMA_Start(&hdma_adc1,(uint32_t)&ADC12_COMMON->CDR,(uint32_t)&ADC12_Result,6);
While I was calibrating each ADC channels, I realized a strange behaviour. I applied a signal to each channel and ADC1 channels were measured as expected. However, when I applied signal to Ch8, ADC2 measured as like there is no signal applied to Ch8. I spent few hours to understand what is going on. I checked ADC settings in CubeMX and I also checked ADC registers about ranking, etc, I checked hardware as well if there is miss routing etc. After sometimes, I realized when I apply a signal to Ch8, Ch8 result is written to Ch9 place in ADC12_Result register. If I applied to signal to Ch18, the result is written to Ch8 place in ADC12_Result register. So, I tested each channel one by one and DMA is written data to wrong places. There is one channel shift. So similarly, Ch 9 -(5)- (14) result is written to Ch 5 (14)-(18) place in SRAM by DMA.
I don't know why is it like that. I have a theory but the reference manual of STM32H742 is not support my theory. My theory is about ADC1 and ADC2 total conversion times are different even they have same settings. ADC1 finishes conversion and generate triggering signal to DMA and DMA starts reading data from ADCx_CDR but ADC2 data is not ready. After DMA reads the results and write in ADC12_Result register, ADC2 finishes its conversion and updated ADCx_CDR. In next cycle ADC1 converts next channel and write the result in ADCx_CDR when previous conversion of ADC2 is already stored. DMA reads ADCx_CDR again and previous result of ADC2 is written to wrong place in ADC12_Result register.
However, the reference manual says: A single DMA request is generated each time both master and slave EOC events have occurred. At that time, the slave ADC converted data is available in the upper half-word of the ADCx_CDR 32-bit register and the master ADC converted data is available in the lower half-word of ADCx_CCR register in Page 987. So, ADC2 should also generate EOC event before DMA request is generated. So, I confused what my problem is. Is it about my code itself or hardware bugs.
I also realized that after reset of the microcontroller DMA writes ADC1 and ADC2 results to correct places in RAM space for awhile. After sometime, DMA starts to write ADC2 results to wrong places and it continuously writes to wrong places after that. I have some screen shuts about it.
So, is there any idea what my problem is and how to solve. I will set separate DMAs for ADC1 and ADC2 and I hope it will solve but before I try it, I would like to ask you. It may be very silly mistake of mine. (By the way, all debug window of DMA and ADC registers were closed. Only I followed ADC12_Result register in the watch window. D- cache is disabled)
Thank you very much indeed.
Regards
