2024-10-11 12:47 AM
Hello Community,
I am using a STM32F411,
2 timer with global interrupt and preemption priority of 0 are executing a timing critical process to bitbang a GPIO port.
4uS timer period
And
a I2C DMA process to update a SSD1306 screen I2C and DMA interrupt have a preemption priority of 14
I am having an issue with the timer bitbang when I sent a message to update the screen.
I thought that lower interrupt priority with take the lead and it seems that it is not the case
Do I miss something ?
Vincent
Solved! Go to Solution.
2024-10-11 01:01 AM - edited 2024-10-11 01:01 AM
Make sure the problem is indeed caused by the priorities, e.g. by toggling pins in the ISRs and checking on oscilloscope for overlap (or lack thereof).
If you've confirmed it, read out and check/post content of NVIC registers (namely NVIC_IPR[]), and SCB_AIRCR to check the PRIGROUP field.
JW
2024-10-11 01:01 AM - edited 2024-10-11 01:01 AM
Make sure the problem is indeed caused by the priorities, e.g. by toggling pins in the ISRs and checking on oscilloscope for overlap (or lack thereof).
If you've confirmed it, read out and check/post content of NVIC registers (namely NVIC_IPR[]), and SCB_AIRCR to check the PRIGROUP field.
JW
2024-10-11 08:03 AM
the issue was a sub priority problem. now fixed
thanks
Vincent