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No 2020 STM32 wishlist

waclawek.jan
Guru

‎2020-06-19 03:29 PM - edited ‎2023-06-18 09:38 PM

This is probably the promised replacement.

[Edit 2023] Link above lead to Ideas, a section mostly ignored by ST (TouchFX crew being exception) and ultimately removed together with content i.e. user wishes when migrating to Khoros [/EDIT]

 

Pity. It's been a nice tradition.

 

JW

 

PS. Following is my 2020 STM32 wishlist. I'm not going to dump it to that new place. Anybody feel free to cherry-pick and post there, if you feel so.

 

 

Others have asked for:

  • more 32-bit timers
  • chips with smaller and/or more prototyping-friendly packages
  • better GPIO/AF matrix
  • use the wide ADC MUX also as input MUX to OPAMP/PGA
  • more transparent software update process (public bug tracker), maybe even open (parts of ) it to external contributions
  • more chips with integrated HS USB PHY
  • shared address/data bus (i.e. stripped-down pin requirement, possibly fitting into 100-pin devices) for SDRAM, as Tiva do https://community.st.com/s/question/0D53W000003xcVSSAY/how-to-configure-sdram-on-100-pin-h7
Labels:
11 REPLIES 11
re.wolff9
Senior

‎2020-06-20 08:36 AM

I don't understand why "AF" has to be separate, AF register could also specify input/output. My suggestion:

AF0: INPUT (GPIO)

AF1: OUTPUT, opendrain, pulldown only (use with pullup).

AF2: OUTPUT, opendrain, pullup only (use with external/internal pulldown).

AF3: OUTPUT, pushpull.

Now make UART_RX an AF in one of the 0bxx00 Alternates. And UART_RX is 0bxx11. Note that the "enable" to the top and bottom output mosfet are (often) simply driven by the lower bits of the AF register. It does break the "AF11 is ETH" rule that is now in place. Anyway, that's how I'd design the AF/GPIO system. Current stuff is quite "spread out" over multiple registers, that could be simplified both for software and for the hardware.

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PMath.4
Senior III

‎2020-06-21 07:33 AM

ST-LINK V3 fixed so it outputs a xtal generated clock on Nucleo PCBs

USB HOST Hub support

Combine H7A3/H743 to get 480MHz part with 1Mb of contiguous memory

More and better example software for Nucleo PCBs. e.g SDMMC using a readily available SDcard socket, QuadSPI flash etc.

DACs and LTDC not sharing pins on 144-pin parts

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gregstm
Senior III

‎2020-06-21 11:53 PM

A few wishes -

  • more timers that can be clocked by the LSE. Ideally most timers should have this as an option.
  • code snippets (as mentioned above), or something similar to help those trying to get a peripheral up and running quickly via registers.
  • some simple way for me to be able to take advantage of the lower power consumption offered by the SMPS, without having to use inductors and flea-sized surface mount packages (for the external regulator). eg. a SOT-23 and some capacitor-only (charge-pump) scheme would suit me better
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re.wolff9
Senior
In response to gregstm

‎2020-06-22 12:12 AM

some simple way for me to be able to take advantage of the lower power consumption offered by the SMPS, without having to use inductors and flea-sized surface mount packages (for the external regulator). eg. a SOT-23 and some capacitor-only (charge-pump) scheme would suit me better



That is not possible. Consider a 1uF capacitor charged to 5V. A second 1uF capacitor is currently discharged. We activate a switch between them and the charge shares between the two caps, 2.5V, both of them. Now consider the energy. E = 0.5 C U^2 = 0.5 * 10^-6 * 25 = 12.5uJ. Good. Now after sharing E = 2 (twocaps) * 0.5 * 10^-6 * 2.5^2 = 6.25uJ : half of what we started with.

So when we use a switching element with a resistance of say 1 Ohm, the equalisation will take roughly 5 microseconds to complete for 99%. Now you can calculate that the ressitor took that 6.25 uJ of energy. If you use an ideal switch (0 Ohms) the losses will end up in the ESR of the capacitors. There is nothing you can do to prevent energy loss.

But yes: Integrated switch mode DCDC would be nice. So now we have an internal 1.2V regulator that generates the power for the core. Integrate the SMPS controller and: there is a quite low current requirement that is known in advance, so quite possible to do this with just one pin and one external component (the inductor).

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gregstm
Senior III

‎2020-06-22 02:41 AM

Oh dear.... reality gets in the way of my dreams. I thought if it was easy to give me the power savings of the SMPS in an easy form it would have been done already. But I am glad that greater minds are working on the problem than me. I added it as a sort of wish in the category of wishing for world peace.... thanks.

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Uwe Bonnes
Principal III

‎2020-06-22 02:52 AM

@re.wolff9

Your proposal does not make sense. Pull Up/Down and Open Drain are properities on top of the peripheral proerities of a GPIO

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re.wolff9
Senior
In response to Uwe Bonnes

‎2020-06-22 03:05 AM

Uwe, First, let me recognize that my GPIO-reform is one that would be incompatible in software, thus now with hundreds of different CPUs already "in the field" this is not realistic to change now.

I agree that the pullup and puldown are simply a bit that cannot be optimized to less than one bit each. (well.... from the four possible options, only three are used, pullup AND pulldown enabled at the same time doesn't really make sense. Although... By enabling them both and finding a 0.5-2.8V analog voltage on the pin you can detect "nothing digital connected")

But I was talking about the actual push-pull output fets. Disable them both, and the pin is an input. Enable only the bottom N-fet and the pin is opendrain. Enable them both and the pin is pushpull output. Again the fourth combination is funny. In this case, I'm not sure if it is documented and/or currently possible, but enabling only the top P-FET will also result in an opendrain output, but now with the other polarity. With the normal opendrain outputs you can make a wired-and (any participant can pull it low, all of them have to drive high to make the signal high). With the other polarity you get the wired or. Anybody can make the signal low.

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RNowa.1
Associate

‎2020-06-23 03:04 AM

Hello

my wish list

  1. More flexible interconections matrix
  2. Multi channel SPI mode for chips like ADS8355 (Dual or quad MISO or MOSI )
  3. Multi channel CS pin (multi dievices on the same SPI)
  4. Timer for delayed CS signal (Dalay for some ADC or DAC's)
  5. More precision, and faster ADC, DAC with PGA,
  6. HW debouncing for mechanical button switches
  7. Faster SPI and I2C (for example 3,4 MHz I2C)
  8. Double buffer mode for DMA (CubeMX config )
  9. Timer triggered dma form most perifery (CubeMX confiq)
  10. Tool in CubeMX for DSP Filter design
  11. Tool in CubeMX for FMAC (G4)

12.Calculators for Timer or ADC bulid in CubeMX ( I want to see usnits such as ms or MSPS directly in CubeMX)

13.New function HAL_Delay_us(), HAL_Delay_ns

14.DARK MODE for all Cube software (vivid white-blue colors are burns my eyes)

15.Better forum (ideal forum looks like this https://www.eevblog.com/forum/projects/)

16.More examples for every periphery and mode

17.Better IDE (simpler and faster IDE without a million unnecessary functions, see Segger, IAR, Keil)

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Asantos
Senior

‎2020-06-23 05:05 AM

H7 wish list:

DTCM-SRAM working with DMA.

Another RMII pinout option from PE7 to PE15 or from PD8 to PD15

Lower cost variants with less flash and AXI-SRAM.

Upgrade the timers and analog peripheras to ones of the STM32G4.

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