Posted on April 18, 2017 at 18:34 Hi
johnr
,
There is no typical rate for updating LPTIMx_ARR and LPTIMx_ARR,but for sure there is maximum rate.
This maxim depends on the APB and LPTIM kernel clock frequency.Based on these 2 flags : ARROK flag and the CMPOK flag in the LPTIM_ISR register, which indicate when the write operation is completed to respectively the LPTIM_ARR register and the LPTIM_CMP register.
- Bit 4 ARROK: Autoreload register update OK
ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR register has been successfully completed. If so, a new one can be initiated.
- Bit 3 CMPOK: Compare register update OK
CMPOK is set by hardware to inform application that the APB bus write operation to the LPTIM_CMP register has been successfully completed. If so, a new one can be initiated.
You should check the ARROk flag is set before any new update.
After a write to the LPTIM_ARR register or the LPTIM_CMP register, a new write operation to the same register can only be performed when the previous write operation is completed. Any successive write before respectively the ARROK flag or the CMPOK flag be set, will lead to unpredictable results.
You may refer to this application note
http://www.st.com/content/ccc/resource/technical/document/application_note/group0/bd/16/1d/53/4a/ef/4e/0e/DM00290631/files/DM002906pdf/jcr:content/translations/en.DM002906pdf
LPTIM low power TIMER, it may be helpful for you. (5.2 PWM generator in STOP2 mode section)
You have also theLPTIM examples in the CubeL4 firmware package whichdescribes how to configure and use LPTIM to count pulses and there isauto-reload each time the counter reaches the maximum value.
STM32Cube_FW_L4_V1.7.0\Projects\STM32L476G_EVAL\Examples\LPTIM\LPTIM_PulseCounter
Hope this helps you.
Imen
When your question is answered, please close this topic by clicking "Accept as Solution".
Thanks
Imen
