Hello,
observed that both the CM4 and CM7 cores are resetting (NUCLEO-H755ZI-Q), whereas it is expected that only the CM4 core should reset due to the Window Watchdog (WWDG2). For verification UART is configured in cm7 printing counter value. observe that after some value the counter is rested to 0, that means both cm4 and cm7 is resting, using stm32cubeide for code flash.
Best Regards
