is it possible to use another output than MCO to generate an arbitrary clock (16.777216MHz) from an internal PLL block?

[Pintoo]

I want to use a different PLL block than PLL1 to leave PLL1 specific to SYSCLK generation; and for example use PLL2 to generate my arbitrary clock.

I see that SAI blocks use for example PLL2 or PLL3 but I don't know if it is possible to make an arbitrary clock at this speed continuously out of these blocks.

[waclawek.jan]

According to RM0456 rev.2 chapter 11.4.6 PLL, the PLLs are fractional, i.e. you might be able to achieve an output frequency close to your target frequency even from 10MHz HSE. We don't know how precise the output has to be and what jitter is tolerable.

> 1/ But can I output this frequency on SAI_SCK or SAI_MCLK for example ?

You should be able to output SAI's input clock (divided by some value, maybe 1) onto SAI_MCLK, but to avoid any unpleasant surprise, you may want to run a quick test on a Nucleo board or similar, before you commit yourself to custom hardware.

JW

[Tesla DeLorean]

It's an ugly frequency, or at least the factors are hard to deal with on most STM32.

Or find a 16,777,216 or 33,554,432 clock for HSE

 T33M554432S001, Abracon

Perhaps a 2.048 MHz or 4.096 would be a better starting point?

If you clock the CPU on a clean integer multiple the TIM could be used.

[Piranha]

Take a look on Si5351 and CS2100. 🙂

[LCE]

Thanks for these!

Interesting that these are advertised as low jitter.

Single freq. MEMS VCXOs have much lower jitter, I recently tested Si515 and SiT3808.

Amazing performance, tested these with the STM32 SAI TX SPDIF and a generated sine, connected to CS8422 (SPDIF RX and SRC) and saw that one's limits concerning noise and THD.