is it possible to use another output than MCO to generate an arbitrary clock (16.777216MHz) from an internal PLL block?

[Pintoo]

I want to use a different PLL block than PLL1 to leave PLL1 specific to SYSCLK generation; and for example use PLL2 to generate my arbitrary clock.

I see that SAI blocks use for example PLL2 or PLL3 but I don't know if it is possible to make an arbitrary clock at this speed continuously out of these blocks.

[Sebastiaan]

Hi,

'Arbitrary' is a confusing word: does it need to be exactly 16.777216 MHz?

For sure you can use the other PLLs and output them on MCO (make sure to select the correct output speed of the GPIOs). So you can get close relatively close to what you want.

If you would share the STM32 MCU type, clock diagram and exact clock requirements, maybe we can give more advice.

[waclawek.jan]

Which STM32?

What hardware? What are the input clocks?

JW

[Muhammed Güler]

You can find crystal and oscillator at the frequency you want.

If you get an oscillator, you can connect it to the MCU and your other equipment with 100 ohm resistors.

If you get crystal you can set HSE for MCO clock source.You can even do this on STM32F0s with MCO outputs.

Or you need to find an MCU (such as H7 Series) with a 2nd PLL circuit and find out which DIVM DIVN DIVP fracn coefficients will get the frequency you want.

[Pintoo]

STM32U585

I think using VCXO at 10MHz and use STM internal PLL to increase the frequency to 16,777216 MHz (2^24Hz).

In my system my need is to have a VCXO to lock an ADC sampling clock to an external time reference, the 10MHz is one of common frequencies found in VCXO components.

[Peter BENSCH]

The PLLs are freely programmable using the given hardware.

In this specific case, PLL2R is the only PLL that clocks the ADCs. As mentioned, their factors and dividers are fixed by hardware and do not allow a direct generation of 2^24Hz from 10MHz (2^7 * 5^7) when the VCXO is connected to HSE.

Regards

/Peter

[Uwe Bonnes]

Having an NCO unit in STM32 could help in some situations.

[Pintoo]

Hi, reading the reference manual m0456 v2 (chapter 11.8.6 RCC clock configuration register 1 RCC_CFGR1)),

I understand that only PLL1_r_ck can be used to drive the MCO output, no possibilities to use other PLLs.

Is my understanding correct?

[Peter BENSCH]

Correct.

[Pintoo]

Correct for the calculus according 10MHz(2^7 * 5^7), so I'll try to find an other low power VCXO.

I need a VCXO to avoid a big jitter on the sampling clock input of ADC, and so keeping a good SNR on ADC.

My ADC is an external ADC, not an internal STM32 ADC.

1/ But can I output this frequency on SAI_SCK or SAI_MCLK for example ?

Because in this case I could segregate the SAI_SCK from SYSCLK value using PLL1 for SYSCLK and PLL2 for SAI_SCK.

MCO output is herited from PLL1, shared with SYSCLK.

2/ May be I could avoid the use of VCXO by pulling the internal MSI RC output through some registers ?