Is it possible to update more than 1 DMA stream on the TIMx_UP DMA request (STM32H7B0)

[Claydonkey]

Is it possible to update more than 1 DMA stream on a "timer up" DMA request (TIMx_UP)?

I am using an STM32H7B0 with the HAL library and can initialize and start the timer/dma interrupt for one DMA request but can more be introduced for the TIMx_UP interrupt?

DMA_HandleTypeDef hdma_timx_up;  
hdma_timx_up.Instance = DMAx_Streamx.
...
HAL_DMA_Init(&hdma_timx_up)
 

start (for GPIO toggling)

HAL_DMA_Start_IT(htimx.hdma[TIM_DMA_ID_UPDATE], (uint32_t) dmaarray, (uint32_t) &(GPIOx->BSRR), dmalen);

[waclawek.jan]

No.

 

The underlying reason is, that for some peripherals - including TIM - the DMA request goes through a latch, which is reset by the DMA/DMAMUX when the request is served. In other words, the first channel which serves the given request clears the latch, with unpredictable results to the second channel connected to the same request. In 'F4, this leads to one of the DMA streams to be frozen entirely (guess how do I know 🙂 ); with DMAMUX the results may be different, but the above warning in the RM indicates, that this is simply something which is not to be attempted.

JW

[Claydonkey]

Thank JW.

I will use multiple timers then.

However can you use the dma_generator to create multiple dma streams that fire on and timup interrupt?

[waclawek.jan]

I'm not sure what do you mean by dma_generator.

In DMAMUX, individual channels can generate events (dmamux_evt, DMAMUX_CxCR.EGE, and some of the events can be selected as triggers to the DMAMUX's Request generator. That supposedly allows to chain DMAMUX channels, and thus generate a chain of requests for several DMA channels/streams. However, I don't use any STM32 with DMAMUX so don't know the intimate details of this.

JW

[AScha.3]

( i dont use DMAMUX also )

but seems possible on H7:

[waclawek.jan]

That just means, that you can use any DMAMUX channel for any request, not that you can use several DMAMUX channels at the same time for the same request. See the RM screenshot I gave above.

JW

[AScha.3]

Thx, Jan , just the "in parallel to all channels" has seduced me to think, maybe...

(because: if in this DMAMUX-thing every out channel has its own state (Flip-Flop (?)) ,

DMA request / DMA served , then it would be possible , as long as only one serves the orignal request source and other just do a mem to mem transfer - or whatever . )

[waclawek.jan]

I see your point, and yes, it could be constructed in this way, but the why would be the warning about not to use one trigger simulteneously by several DMAMUX channels.

Yes, I would love to hear somebody who actually knows the STM32 internals to chime in, but that won't happen.

JW

[Tesla DeLorean]

Could one use CCRx = 0 triggers as secondary, tertiary proxies for UPDATE trigger? Phase alignment here would be simpler than using multiple timers and synchronizing them.

[waclawek.jan]

Just as a curiosity, in the 'H7Ax/7Bx, TIM4_CH4 is not connected to DMAMUX1 requests.

JW