cancel
Showing results for 
Search instead for 
Did you mean: 

Is it possible to configure TIM1, 2, 3 and 17 as both master and slave?

AB
Associate II

Purpose is to generate 4 mutually phase shifted PWMs. Regular master/slave mode will require 8 timers in that case (right?). So thought of using the following, if possible:

TIM1 = master to TIM2, TIM2 = slave of TIM1 and master to TIM3, TIM3 = slave of TIM2 and master to TIM17, TIM17 = slave of TIM3 (Will have to make sure there is no interlock which prevents TIMx and TIMy to be in master slave mode). Device planning to use is: STM32F334xxx.

HRTIMs already used up.

14 REPLIES 14
T J
Lead

you need to run a state machine under timer interrupt.

Super smooth at 150KHz if you need it...

if you don't want any issues, dont use task switching.

Singh.Harjit
Senior II

​You can have one timer be the master and the others be the slaves.

Looking at the block diagram for timer 17 in reference manual (Figure 213), timer 17 cannot be a slave to any other timers.

I'll walk you through how to synchronize timer 1, 2 and 3 and if you can redo your timer assignments, you might be able to find a solution.

The TIMx_CR2 register's MMS field selects which event on a timer generates an event on that timer TRGO (or TRGO2 if it has one) signal.

The TIMx_SMCR register's TS field selects the trigger event source that timer will listen to.

The TIMx_SMCR register's SMS field select what that timer does when it gets the trigger / event.

Since we want timer 1 to be the master, configure its TRGO (in TIM1_CR2) to generate a TRGO when timer 1 is enabled (MMS[2:0] = 001

NOTE: The reference manual has an error on page 445 and it says: Bits 6:4 MMS[1:0]. Clearly it should say Bits 6:4 MMS[2:0]

Then, for timer 2 and 3, configure TIM2_SMCR and TIM3_SMCR, SMS[3:0] to 0110 to enable them when they receive an active edge on TRGI.

To select which signal to use for TRGI, we want timer 1 which using table 73 is ITR0 which means set TS[2:0] = 000

If for example, you could use timer 15 instead of timer 17, you will notice that it only has internal trigger connections to timer 2, 4, 16 OC1 and 17 OC2 (table 76). So, you cannot have timer 1 trigger timer 15!

What would could do is make timer 1, 3 and 15 slaves and timer 2 the master. Now, when you enable timer 2, the others will be simultaneously enabled. 

I believe you don't need linked timers at all, and the above waveform can be achieved by using two complementary channels on TIM1. Deadtime between complementary channels is given by TIMx_BDTR.DTG, and I believe the both parts of complementary channel going high can be achieved by having OSSR=1, setting the mode to forced active (that brings the "straight" part high if CCxP=0), disabling the complementary part by CCxNE=0 and setting its polarity by CCxNP=1.

JW

Imen.D
ST Employee

Hello,

Thank you @Singh.Harjit​  to report reference manual errors, I will raise this internally for correction.

Kind Regards,

Imen

When your question is answered, please close this topic by clicking "Accept as Solution".
Thanks
Imen
AB
Associate II

Thanks @Singh.Harjit​  and @Community member​  both for the answers. Its a new design and I am just not comfortable restricting the PWMs to be strictly complementary, as the PWM pattern might change later on. Thus, I am going with Harjits solution.