Is here any reason for using HSE crystal with STM32L431 ?

[maple]

Every L4 board that I've seen had footprint for HSE crystal routed but not populated. As I understand it is because MSI has automatic calibration on LSE clock. In my latest design I did the same - reserved place for HSE but marked it DNP. The 32.768kHz NX3215SA crystal has 20ppm tolerance, while 8MHz NX3225GD has 50ppm. So, unless I am missing something obvious, I am getting better frequency tolerance without HSE crystal.

Now I am working on reducing board size for new revision, and unused HSE footprint takes a lot of PCB space. Is there any reason for using it at all? So far everything works great on LSE crystal alone.

[Uwe Bonnes]

There is few specified data what can be achieved with LSE stabilized MSI. Only the front page tells:

­ "Internal multispeed 100 kHz to 48 MHz

 oscillator, auto-trimmed by LSE (better than

 ±0.25 % accuracy)"

So if you can live with up to 0.25 % tolerance (2500 ppm tolerance, all fine. If you need a better clock, e,g for some freuency measurement, things get more difficult.

[LMI2]

Ethetnet needs an accurate clock and I think so do USB. Serial bus has some limits too

[TDK]

If you're not using an LSE crystal and you want an accurate clock. Note that some 8MHz crystals have tighter tolerance than 20ppm, so it's not always a guarantee that the LSE will be more accurate.

But if you're already using the LSE and derive your system clock from there, no I don't see any reason to also add an HSE to the mix.

[Piranha]

I2C and SPI are synchronous and doesn't care for frequency accuracy. Asynchronous UART cares, but HSI/MSI tolerance is enough for it. HSI48 can be synchronized to LSE or to USB SOF for completely crystal-less operation. Do you need accurate RTC? Look to it from the other side - do you need any crystal at all?

P.S. https://uk.farnell.com/w/c/crystals-oscillators/crystals?frequency-stability-pos-=10ppm&frequency-tolerance-pos-=10ppm&range=inc-in-stock&sort=P_PRICE

[maple]

To clarify the requirements, the application uses UART at 3Mbps and CAN at 1Mbps. We will be using RTC for logging purposes, which does not require high precision. So far we did not have any problems with LSE crystal only, but it was kinda nice to know that we can mount HSE crystal if it becomes necessary. Getting rid of the footprint will make it impossible but will reduce PCB by about 10%. This is the reason for this question.

Also, I found that reference to 0.25% accuracy @Uwe Bonnes​  mentioned. Don't know how I missed it to begin with. In my calculations I relied on datasheet 48.005 MHz for PLL with LSE, which basically says there is "built-in" 0.01% frequency offset. With 20 ppm of LSE crystal factored in I expected about 124 ppm MSI frequency tolerance, while frequency stability (temperature and voltage) being equal to those of a crystal.

[waclawek.jan]

> 48.005 MHz for PLL with LSE, which basically says there is "built-in" 0.01% frequency offset

32768 * 1464 = 47972352

32768 * 1465 = 48005120

32768 * 1466 = 48037888

> With 20 ppm of LSE crystal factored in I expected about 124 ppm MSI frequency tolerance,

How did you come to the 124ppm? Why would PLL change the relative error?

Or did you simply add those cca 5000Hz/104ppm? That would then be +127 +87 ppm, rather than +-127ppm.

PLL adds jitter, though. There are some parameters in the DS, but not much clear to me.

Also, note, that you can quite easily "spoil" a nominally +-20ppm crystal with incorrect burden capacitors or layout. OTOH, you can "fine-tune" it, too; although that's exceedingly rare these days (RTC can be corrected digitally). You might be even able to deliberately "downtune" the crystal those cca 100ppm.

The 0.25% is the value required for USB FS device. I've met already such dumb specs with other chips, where the DS states not the true values from the device's characterization, but values required by some standard, or just simply values copied from an "industry standard" version of the same chip from other manufacturer - even if those parameters are way worse than the device's capabilities are.

JW

[maple]

@Community member​ 

Yes, I simply added that offset. Not much of a difference with your number, compared to 2500 ppm. I have no idea how PLL affects the tolerance.

> where the DS states not the true values from the device's characterization, but values required by some standard

If that is indeed the case, which I hope it is, then I think I'll follow advice by @TDK​  and others and get rid of HSE footprint.

Thank's for help, everybody!

[gregstm]

I try to do all my accurate audio timing with just the LSE (it uses minimal space and now you can get amazingly small packages for the crystal). However I did need to use a HSE crystal when I created video signals for a large TV (when I used the MSI+PLL, the display was extremely jittery )