Inconsistent docu of FDCAN valid SJW values in STM32G4 Reference Manual

[MScho.1]

Hello,

I'm confused about the documentation of the (Re)Synchronization Jump Width SJW for FDCAN in the RM0440 of STM32G4. There is a difference in docu for valid values for SJW between

1. section "43.3.1 Bit Timing": one to four quanta
2. section "43.4.7 FDCAN nominal bit timing...": NSJW valid values are 0 to 127 quanta

Could you clarify which statement is true? Are NSJW values >4 operational?

Thanks!

[Imen.D]

Hello @MScho.1​ ,

The first value (four time quanta) is the suggested value to be put in the driver for the IP to resync to the optimal sampling point assuming that the BS1 and BS2 is bigger than the SJW.

In case of a high FDCAN frequency and a low FDCAN rate, for example FDCAN Freq = 80 Mhz and a Rate of 1 Khz, the BS1 and BS2 could be set to 384.

If a keep an SJW to low the system will take a long time to converge to the optimum sampling point (up to BS1 / SJW), this is why in this case it is more efficient to increase the SJW in the driver.

I hope that is clear now for you.

I raised your feedback internally to improve the doc and clarify this point in the next releases.

Best Regards,

Imen

[MScho.1]

Hi Imen,

thanks for the reply.

I'm afraid I havent't fully understood. Sticking to your example of FDCAN freq 80MHz and bit rate of 1kHz. This would require 800 time quanta, so this cannot be achieved with the maximum of BS1+BS2 = 384.

Let me clarify my question and let's switch to realistic example to set a correct discussion basis: FDCAN freq 80MHz, bit rate 1MHz. This requires 80 time quanta, so setting BS1=39 and BS2=38 will be a possible configuration with #quanta = Sync + (BS1+1) + (BS2+1) = 1 + 40 + 39 = 80.

Now my question is about the possible values of SJW. In principle the register for SJW allows me to set any value between 0 to 127. Reasonable values in our example are of course only 0 to 38, since they need to be smaller than BS1 and BS2 respectively. The thing I'm confused about is that the doc that says "SJW is programmable between one and four quanta", although the register lets me program much higher values. So my question is: What happens if I set SJW to any value larger than 4, lets say 30? Will the jump width used by the controller be really 30+1 or is there some internal hidden limitation to 4 quanta?

I hope this clarifies my question.

[Imen.D · Accepted solution]

Hi @MScho.1​ ,

I mean: BS1=384 and BS2=384 with FDCAN Clk =80Mhz => 100Kbps (not 1Kbps) => need at least 127 for SJW to no take too much time for convergence.

Yes, your SJW could be set between 1 and 30 and there is no hidden mechanism to limit to 4 the jump.

We will clarify the used case using only 4 in SJW which is just an example not a constraint. The constraint is the one define in the register section (max=127).

Best Regards,

Imen

[MScho.1]

Thanks @Imen DAHMEN​ for comments, now it became clear to me :)

Sorry for being nit-picky: For the FDCAN_NBTP register the values of BS1 are limited to 0...255 and for BS2 to 0...127. That's why I was not a friend of your example with 80MHz and 100kHz bit rate that requires BS1 and BS2 values larger than these limits ;)