How to sync ADC sampling at 192K to DAC output

[Robmar]

On STM32F407V-Disc the divisions don't work out for an 192KHz Timer trigger for the ADC, so sampling runs a bit slower or faster, the problem is that the Cirrus DAC audio chip cannot be set to match the sample rate, so I get buffer sync drift, audio is clear but at the end of every second there is a "scrrrr, scrrr" noise as the DAC buffer end is overwritten while it should have reached the start, but the clock issue delays it... I think that's it at least.

I down-sample the 192.2KHz to 48.05KHz, but with no way apparently to sync the ADC and DAC streams I have tried to use HAL_I2S_Transmit_DMA() to send the samples at the required 48KHz rate, but when called from HAL_I2S_TxHalfCpltCallback it only works once!

I can get HAL_I2S_TxHalfCpltCallback to run continuous, but can't see how to reset the DMA reading to sync to the data rate coming in at 192.2K/4. I need to reset the I2S DMA read to the start of my audio samples buffer in continuous mode. This will lock the audio playback to the incoming sample rate.

There would be 5uS of audio missing every 666uS using sample buffer realignment but I don't think it would be detectable.

All ideas welcome, its been a stressy couple of days to say the least!

[Robmar]

Not so easy because changing the xtal frequency will fix the ADC frequency but then take the DAC off frequency. We´ll have to dig into it, maybe add an external clock reference for the ADC, which is bad because it ups product costs in a very competitive market.

[LCE]

I was curious and just started the CubeMX clock configurator for the F407...

Oh my, that one is limited compared to the F7, and even more the H7.

If you do not need the exact 48 MHz (for USB?) and you can live with a CPU clock of only 144.384 MHz, then you could take 12.288 MHz as HSE, then ADC and I2S can get to exactly 48 / 192 kHz.

Too many ifs I guess.

Do you use the audio DAC only for that ADC data?

[Robmar]

Thanks for taking the time, but the app is already overloading the MCU, so a speed reduction is out of the question. ADC data is heavily DSP processed, then down-sampled to 48KHz (or nearly).

What we need is a 407VG with more memory and a 400 MHz or better clock, with all the same peripherals, around the same price or maybe 20 percent higher.

[AScha.3]

so the STM32H750VBT6 would be nice...

[Robmar]

That might do it, ​I can use the I2S complete interrupt to transfer the compressed samples, after the ADC interrupt averages 2 samples every 984 sampled, as there's 13% of an extra sample every 128 ADC samples. There's still a tracking error but it may be unnoticeable.