How to read STM32H7 SRAM ECC status?

[Gpeti]

I want to periodically check the state of the RAM ECC detection in my firmware on a STM32H753.

The ECC mechanism is well described in the Reference Manual for the Flash but not very well (in my opinion) for the RAM.

I've seen that there are dedicated interrupts for RAM ECC but it is not clear if they are triggered for single error or double error ?

Also, why a dedicated interrupt and not a BusFault (like it is done on the Flash if I understood correctly ?)

Also , I don't want to get interrupted for a single error (that is properly corrected). Instead I want to get the status periodically and log the error somewhere. What is the register to read to check whether a single error happened ?

[berendi]

RAMECC status and interrupt flags are defined in the stm32h7??xx.h headers, and there are some code examples in stm32h7xx_hal_ramecc.h/.c

Apparently it's possible to independently mask single/double ecc fault interrupts.

There is application note AN5342 as well, but it's not very helpful.

[Gpeti]

Thank you, I didn't notice there was a HAL. What is incredible is that these registers RAMECC_*** are not defined in the Ref Manual or Prog Manual !!

Are we supposed to understand how a peripheral works by reading the HAL code ?

[waclawek.jan]

> What is incredible is that these registers RAMECC_*** are not defined in the Ref Manual or Prog Manual !!

@Imen DAHMEN​  can you please have a look at this? Cube/HAL is not supposed to be the primary source of information.

Thanks,

JW

[Pavel A.]

Here's the example:

https://github.com/STMicroelectronics/STM32CubeH7/tree/master/Projects/NUCLEO-H745ZI-Q/Examples/RAMECC/RAMECC_ErrorCount

[Imen.D · Accepted solution]

Hello,

RAMECC registers section will be available (in few weeks) in the next release of RM0433, with same RAM ECC chapter that it's already in RM0399 (STM32H745/755 and STM32H747/757).

Best Regards,

Imen

[Gpeti]

Thank you. I didn't think to have a look to other STM32H7 ref manuals.

[waclawek.jan]

Thanks, Imen.

Jan

[Gpeti]

Imen, I've read the RAM ECC section in STM32H747 ref manual. I understood that a double error detection in the RAM does not generate a BusFault, as it is done for Flash ECC. It only generates an interrupt (if enabled). Is it correct ?