How to configure "Delay between 2 sampling phases" on the STM32G431

[Clavin-z]

板：STM32G431 NUCLEO-64
我的目标是在 ADC1 和 ADC2 上实现 4 MSPS 的采样率。通过使用交错采样，我的目标是获得 8 MSPS 的有效采样率。虽然我知道这可能与数据表中针对多通道 ADC作的声明限制不严格一致，但我相信这种差异与我遇到的问题没有直接关系。

根据数据表中的图1、ADC 时钟应低于 52 MHz。

图 1

在我的设置中，我在交错模式下使用 TIM + DMA + ADC，配置如下：

• 定时器触发频率：4 MHz

• ADC 分辨率：12 位

• ADC 时钟：60 MHz

• 采样时间：2.5 次循环

我的输入信号是由板载 DAC 生成的连续正弦波，频率为 50 kHz。

在查看与 timing calculations相关的 datasheet 部分后，总转换时间似乎应该在7.5 cycles 左右。但是，STM32CubeMX 只允许采样时间设置介于 1 和 12 之间的整数值，因此我选择了 7 个周期。

以下是我观察到的：

• 当我将“Delay between 2 sampling phases”设置为 7 个周期时，采样间隔看起来不规则，并且与预期的交错模式不匹配（参见图 2）。

• 当我将“Delay between 2 sampling phases”设置为 12 个周期时，得到的采样间隔看起来是均匀分布的（参见图 3）。

图 2

Figure 3

What I want to understand is:
What is the correct value to set for “Delay between 2 sampling phases” to achieve ideal interleaved sampling with evenly spaced samples?

[Sarra.S]

Hello @Clavin-z, please write your posts in English to help ensure that more community members can understand and assist you effectively! 

-Post translated in English-

**Board:** STM32G431 NUCLEO-64

My goal is to achieve a sampling rate of 4 MSPS on ADC1 and ADC2. By using interleaved sampling, I aim to obtain an effective sampling rate of 8 MSPS. Although I am aware that this might not strictly align with the datasheet's stated limitations for multi-channel ADCs, I believe this discrepancy is not directly related to the issues I am encountering.

According to Figure 1 in the datasheet, the ADC clock should be below 52 MHz.

**Figure 1**

In my setup, I am using TIM + DMA + ADC in interleaved mode, configured as follows:

- Timer trigger frequency: 4 MHz
- ADC resolution: 12-bit
- ADC clock: 60 MHz
- Sampling time: 2.5 cycles

My input signal is a continuous sine wave generated by the onboard DAC, with a frequency of 50 kHz.

After reviewing the datasheet section related to timing calculations, the total conversion time seems to be around 7.5 cycles. However, STM32CubeMX only allows the sampling time to be set to integer values between 1 and 12, so I chose 7 cycles.

Here is what I observed:

- When I set the "Delay between 2 sampling phases" to 7 cycles, the sampling intervals appear irregular and do not match the expected interleaved pattern (see Figure 2).

- When I set the "Delay between 2 sampling phases" to 12 cycles, the resulting sampling intervals appear evenly distributed (see Figure 3).

What I want to understand is: What is the correct value to set for "Delay between 2 sampling phases" to achieve ideal interleaved sampling with evenly spaced samples?

To achieve ideal interleaved sampling with evenly spaced samples, the "Delay between 2 sampling phases" should be set such that the total time between samples from ADC1 and ADC2 matches the desired effective sampling interval. Given your configuration and observations, setting the delay to 12 cycles seems to provide evenly distributed intervals, which suggests it might be the correct setting. However, ensure that this setting aligns with the ADC clock and trigger frequency to maintain the desired overall sampling rate.

[Sarra.S · Accepted solution]

Could you check these articles on how to configure ADC interleaved mode: 

ADC interleaved mode (1/2): How to improve ADC sampling rate

ADC interleaved mode (2/2): Hands-On STM32CubeIDE project