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FMC: How to delay chip select?


I should combine STM32F479 with PROFIBUS-DP ASIC SCP4-2

2023-09-25 10_32_07-Window.png

 The chip is aged. And requires delay of at least 30ns (by 3v3) between address and cs. Our previous design was based on SAM4S and their CPUs are offerring register to program such delays. In STM32F4 reference all the pictures suggesting that cs is always phase synchronous to AB change.


Did I overlooked something? How to deal with this?


The STM32 FMC is far from being perfect with regard to flexibility of provided signals, their polarities and timing. It is what it is.

So here, you won't be able to get away without external glue logic.

You can try to delay the CS signal e.g. using a shift register clocked from the system clock. Maybe a scheme could be devised where the NEx is fed into a timer's channel which would provide the delay; but this would need some more thought.

Or maybe Mode D could be employed, with a couple of gates combining NADV and NEx into the required chipselect waveform.



What about simply using another GPIO as CS? 
Okay, DMA mode will be problematic...

Billy OWEN
ST Employee

Hi @AlexKern 


The forum moderator had marked your post as needing a little more investigation and direct support. An online support case has been created on your behalf, please stand by for just a moment and you will hear from us.




Hi @Billy OWEN ,

Please discuss this - and other topics opened in public forum - publicly, for benefit of both us and ST.