External load capacity calculation

[ame]

Hello All,

I'm a bit stuck on the calculation of the external load capacitances on a STM32F205, regarding the LSE Oscillator for 32.768kHz.

In the AN2867 there is the following formula:

When assuming that CL1 and CL2 are the same, the formula could be simplified to this:

The stray capacitance Cs is given by the sum of the pin capacitance and the PCB. In the STM32F205 datasheet there is a note where you can use 10pF as rough estimate for the stray capacitance.

So regarding this information and the formula above, the load capacity of the selected crystal must always be greater than 10pF (Cext will be 0pF if Cl is 10pF).

And here I'm stuck now. Because in the list of compatible crystal oscillators in the AN2867 there is no F2 compatible oscillator with a load capacity above 10pF. What I see are some oscillators with a load capacity below 10pF, but how could that be? When following the formula I have to add an negative external capacity...

Best regards

Al

[Javier1]

Your title is missleading, maybe add "HSE External load capacity calculation"

take a look at this:

https://community.st.com/s/question/0D53W000008kCYqSAM/stm32f103rct6-hse-and-lse-crystal-selection

[Javier1]

and answering your question i think youre swapping capacitance names.

Check your naming convention, make sure Cext means what you think it means

[ame]

Hi Javier,

thanks for your comment. See below what I mean by Cext:

I hope the image is not to small. For me, Cext is the value for CL1 and CL2. It's the external load capacity needed to trim the total CL value to the desired value requested by the oscillator datasheet. In the end, I have to place Cext on the place of CL1 and CL2 in my schematics.

Regarding your link to the crystal selection I see that there was used 4pF as stray-capacitance, even the datasheet of the uC is also here stating an input capacity of 5pF (typical). Or do I miscalculate the stray-capacitance?

[TDK]

Your assumptions are correct, however 10pF seems high for the stray capacitance. It's usually closer to 4-5pF in my experience.

You could look up an ST schematic with a STM32F205 chip and see what they used for C_S.

[ame]

Hi @TDK​ , thanks for your message.

I've checked with the MB786 where the CL is 6pF and Cext is 6.8pF, resulting in a Cs of 2.6pF. I've also checked the MB1137 where CL is 6pF and Cext is 2.7pF, resulting in a Cs of 4.65pF.

So I can't really get to an conclusion here, but maybe I see this to narrow. Meaning that the rough 10pF given by the datasheet is indeed only a rough value and the external load capacitors are only needed for tuning to the exact frequency.

The main concerns on the oscillator will be the gain margin to be above 5 so that the oscillator is guaranteed to be working.

Does this make sense to you?

[TDK · Accepted solution]

It is an estimate because it depends on your layout. I’ve always used 4pF as an estimate and never had issues but I’ve never made a board with the F2 series.
There is definitely some wiggle room. I would copy a known ST board if you can.

[Piranha]

From my experience two layer boards typically have a Cs of 1-2 pF. Four and more layer boards will have something in a range of 3-5 pF.