Ethernet driver initialization fails in the STM32F217VGT6

[sahana-raghavan-ms]

Hello,

I'm currently working on a project that includes integrating a real-time operating system into the STM32F217VGT6. I created a project for the STM32F217VGT6 MCU with FreeRTOS as the middleware in the STM32CubeIDE v1.13.0. The code generated in 'Src/main.c' has the following problem:

The generated function 'MX_ETH_Init()' calls 'HAL_ETH_Init()'. If 'HAL_ETH_Init()' returns status other than 'HAL_OK', 'MX_ETH_Init()' calls '_Error_Handler()', which (of course) does not return.
At the moment I am not sure how to proceed.

Thank you.

Sincerely,
Sahana Raghavan

[LCE]

Are you using a custom board or some evaluation board?

Debug it and find the exact function / point where the error occurs.

Maybe the PHY (which one?) has not the correct address setting?

[sahana-raghavan-ms]

Yes it is a custom board. Afer debugging, I found that the HAL_ETH_Init() function (in the MX_ETH_Init()) calls the Error_Handler() function.
I am not sure what you mean. Please tell me how to check if it is the correct address and change the address.

[LCE]

There must be an address bit in some MDIO register (I don't know the F217), and your PHY probably has a pin, if it is the LAN8742 it is pin 10, which should have a pull-up or pull-down resistor.

Debug some more... you should find something more specific which part in HAL_ETH_Init() causes the failure.

Or maybe other MDIO settings (for PHY control & setup) are not correct? Like clock divider.

[sahana-raghavan-ms]

The problem is from this function in the HAL_ETH_Init():

while (((heth->Instance)->DMABMR & ETH_DMABMR_SR) != (uint32_t)RESET)

{

/* Check for the Timeout */

if ((HAL_GetTick() - tickstart) > ETH_TIMEOUT_SWRESET)

{

heth->State = HAL_ETH_STATE_TIMEOUT;

/* Process Unlocked */

__HAL_UNLOCK(heth);

/* Note: The SWR is not performed if the ETH_RX_CLK or the ETH_TX_CLK are

not available, please check your external PHY or the IO configuration */

return HAL_TIMEOUT;

}

}

The PHY is LAN8472A.

[LCE]

So software reset doesn't work, check the reference manual upon what that relies, then check what the comment says, if there's a clock to or from the PHY, whatever your settings should be, if the clock source should be the STM or the PHY :

/* Note: The SWR is not performed if the ETH_RX_CLK or the ETH_TX_CLK are not available, please check your external PHY or the IO configuration */