Enabling instruction prefetch in the HAL (potential bug)

[GG.2]

Hello,

According to the reference manual RM0456 7.3.3:

"Prefetch is enabled by setting PRFTEN in FLASH_ACR.
PRFTEN must be set only if at least one wait state is needed to access the flash memory"

Compared to that I've seen that in the U5 HAL, in the function HAL_Init() there is a call to `__HAL_FLASH_PREFETCH_BUFFER_ENABLE()` (when `PREFETCH_ENABLE` is defined).

This means that prefetch might be enabled even when there are 0 wait states to access flash memory (because this is not enforced), contradicting what the reference manual says.

Is it intentional? or might cause undefined behavior?

Thank you

[Tesla DeLorean]

Probably less consequential if the Flash can service with no delay, but yes language here seems awkward and could.be explained more clearly and reasoned. @Sarra.S 

[Sarra.S]

Hello @GG.2, @Tesla DeLorean, 

Thank you for bringing this question to my attention! 

>>This means that prefetch might be enabled even when there are 0 wait states to access flash memory 

This case is not applicable in U5 Flash examples, in fact, all the examples run at 160MHz, according to this frequency, there are 4 wait states (Check RM) : 

So prefetch has to be enabled, and PRFTEN must be set since there is more than 1 wait state needed. 

I hope this is much more clear.  

[GG.2]

The problem is that I'm running my own code, not the examples, and the HAL should not assume the HCLK frequency... In my case I run at 12MHZ range 4 with 0 WS

[SofLit · Accepted solution]

Hello,

That' true the macro is called in the HAL: 

HAL_StatusTypeDef HAL_Init(void)
{
/* Configure Flash prefetch */
#if (PREFETCH_ENABLE != 0U)
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
#endif /* PREFETCH_ENABLE */

But the software flag is activated in the example itself in stm32u5xx_hal_conf.h file:

#define PREFETCH_ENABLE 1U /*!< Enable prefetch */

stm32u5xx_hal_conf.h file is not part of the HAL but part of your example or project.

So you need to set it to 0 in your case.

[Tesla DeLorean]

No, I think the question relates to the 0 WS line, and how exactly the FLASH and Prefetch pathing is working, or required to work.

I think a white paper illustrating some of the plumbing, clocking and core connectivity would help show what needs to be enabled, or not, and why, as it relates to reads of memory, and data flows.