Do I need an external cap on vref+ when using internal vref buffer?

[PRitt.1]

I am using the STM32G0B1 and would like to use the internal VREF buffer to drive VREF+ for the DAC and ADCs.  I found the following presentation detailing its use:

https://www.st.com/resource/en/product_training/STM32G0-Analog-Voltage-reference-buffer-VREFBUF.pdf

There are two modes where the internal voltage reference is enabled, I assume I want the one with HIZ == 0 but I am curious what the Hold mode is?

The doc has a bullet that says "Requires external capacitance on VREF+ pin" and later says "the voltage is held with the external capacitor" - is that only for the Hold mode or do I need it in both modes?

Thanks!

Phil

[Jaroslav JANOS]

Hello Phil,

yes, in your case you need to connect this external capacitor to VREF+ pin - to be precise, it is recommended to connect 100 nF and 1uF capacitors in parallel. In the Hold mode, the voltage on the VREF+ pin is dependent only on voltage of these capacitors, because the analog switch between VREFBUF and VREF+ pin is open.

For further information including examples of VREFBUF applications, please refer to AN5690.

BR,

Jaroslav

[waclawek.jan]

Hi Jaroslav,

Interesting appnote, thanks.

However, section 4 is confusing to me. In fact, it does not in any way highlight features of VREFBUF output and IMO should be removed from that AN.

(Also, 4.4 is, to put it mildly, embarassing: the R/T curve of NTC resistors is nonlinear, and constants to fit that curve are provided by the NTCs vendor.)

Instead, I'd recommend to expand the AN with more detailed and meticulously arranged information on VREFBUF itself. For example, Fig.1 contains an "optional 1kOhm RLOAD" - it should be stressed that that's a max. 1kOhm (is it?) load and it's not something you want to add just for sake of loading the output, but provision to output reference if needed for external circuitry.

I'd also like to see a discussion on the precision and temperature/voltage/long-term stability of both the bandgap reference and the dividers/switches.

I'd also like to see block diagram including the HOLD switch.

The remark about VREF+ being bonded to VDDA in small-pin-count packages is okay, but the formulation "is not available" (which is also in the DS) is IMO more a marketing wording and not descriptive enough for engineering. It sounds like "VREFBUF is simply not there in these models", which implies also "...so it's OK to use a common code with other models which enable it". Rather, it should be formulated so that "enabling VREFBUF is forbidden in these models" or similarly.

Also, I'd like to read more details about how exactly VRR achieves that it "is set when the VREFBUF output voltage accuracy is 1% from the selected voltage range".

Also, in the TRIM treatise, I'm confused about using the internal VREFINT source. Is it independent from the VREFBUF's bandgap? Is it significantly better?

Also, I'd like to read more details about the "hold" feature, it's intended usage modes, it's shortcomings etc. I faintly recall reading about it in some other AN, maybe the 'G4-specific ADC AN was it? If so, it definitively belongs here too.

Oh, and please provide the appnote in normal black-and-white, instead of the ugly and hard-to-read modern-feel-and-look.

Thanks,

JW

@Jaroslav JANOS​ 

[Jaroslav JANOS]

Hi @Community member​ ,

thank you for your valuable feedback, I will forward it to people responsible for this AN. I agree it is not perfect, but might by helpful - as in this case. I assume your comment was just a feedback/proposal for improvement (please correct me if I am wrong), so I won't fully answer your questions.

Concerning section 4, IMO it describes how to achieve specific tasks using the VREFBUF peripheral, which is what ST's ANs are (or at least should be) about. So I don't think it should be removed, just updated.

For the 4.4 I agree that the quality of graphs is rather poor. Anyway the scale is logarithmic, so the R/T curve is nonlinear.

Next, Figure 1 and the 1kOhm load. No, this is not the maximum, it is just an example of optional/possible external load. Maximum load of VREFBUF is product-specific and is therefore present in the corresponding datasheets. For example, maximum load for G4 is something about 6 mA, for some other product it is 4 mA etc.

Concerning the "is not available" wording for small-pin-count packages, I agree with you that this could be mentioned also in the DS, still in the reference manuals you can find "is not available and must be kept disabled" which is what you probably meant.

About the "how exactly VRR achieves ***", I think it is sort of a confidential thing and it won't be shared publicly. Anyway do not hesitate to contact us if you encounter some out-of-sepc behavior, i. e. voltage being off by more than 1 % after VRR=1.

For the hold mode, I cannot find this AN you are referring to... But still yes, better description of the hold mode could have been included.

And the last point, look of the AN. I think this is a matter of opinion. It is in use for few years for all new ST products and I don't think there were so many negative feedbacks to come back to black-and-white.

BR,

Jaroslav

[waclawek.jan]

Hi Jaroslav,

Thanks for taking time to reply to my ramblings. Yes, it's just that, ramblings, maybe it's not worth the attention you gave to it; thanks nonetheless.

> AN... might by helpful

No doubt it *is* helpful. There are way too few STM32 ANs.

> section 4

We won't agree on that. Except for 4.3 (which is okay but a rather trivial one), in those sections VREFBUF plays no other role than any VREF+ source.

I'd recommend to replace it with examples which highlight VREFBUF specifically. What about showing that change of output voltage changes the achievable minimum voltage step? Together with an example code switching between output voltages (highlighting the need for the bleed step), and a nice oscilloscope waveform of output voltrage rise, showing tSTART, its dependence on load R and load C, and the exact time how it reaches the specified output voltage, together with the moment when VRR is set to 1.

Or what about highlighting improved precision/noise, as compared to VREF+ being connected to VDD/VDDA supplied from some bog standard LDO? That might be a nice case also to exhibit Iline_reg and PSRR of VREFBUF in measured graphs. Subsequently, an experiment with Iload_reg would be nice to see.

Those are IMO the important features of VREFBUF itself. Leave ADC and DAC-specific issues to ADC and DAC appnotes.

> 4.4,

Yes, I've overlooked the lin/log nature of the T/R graph, so I was wrong and hereby I retract what I've said (...a slibuji co jsem slibil :) ) But I maintain, that as a whole it's still not appropriate for VREFBUF appnote, as per discussion above.

> Figure 1 and the 1kOhm load

To me, Fig.1 looks much like a recommended application circuit (and if it's not, this appnote would deserve one).

Btw. I've looked at the 'G4 DS, and noticed that while Iload is indeed max. 6.5mA, Iload_reg is guaranteed only up to 4mA. It's details like these which ought to be discussed in somewhat more detail in a specialized AN such as this.

> "how exactly VRR achieves ***", I think it is sort of a confidential thing

Okay. So let me rephrase: would I load the output improperly, too heavily, would VRR be never set? (i.e. can it be used for indication of failure for external reasons?) Also, can it be used for indication of output failure (again say due to some improper loading) *after* it has been set? It's absolutely okay if not, just it's a nice thing to know.

> For the hold mode, I cannot find this AN you are referring to...

Neither can I :( . I was under the impression that I've seen more about it in AN5346 or AN5310, but only latter contains reference to VREFBUF and that's just more-less verbatim copy from RM, no extra info on hold mode... I might've just imagined I've seen such AN, sorry.

Nevertheless, for hold mode, besides concise description (and addition of the switch to the internal "schematics"), a section-4 example for this mode would be very interesting, too, together with example analysis in particular application and waveform pictures.

---

Oh, and one more thing, which is IMO missing from this AN: even if it might seem that it's a self-evident thing, IMO it should say clearly and loudly, that VREFBUF has a clock which has to be enabled in RCC - either through RCC_APB4ENR.VREFEN, or RCC_APBENR2.SYSCFGEN, or maybe other bit in other families.

--

> It is in use for few years for all new ST products and I don't think there were so many negative feedbacks to come back to black-and-white.

Can you put the number of negative (e.g. see the link I gave) and positive feedbacks in ratio?

Most users don't complain publicly. You have to ask for opinion.

- -

Thanks again for your time!

Jan

@Jaroslav JANOS​ 

PS.

[Jaroslav JANOS]

Hi Jan,

I really do value your feedback on this AN! Now I am even considering getting involved in it :) 

> section 4

Sorry, I also made a mistake and judged the content just from the title and last paragraph while not reading the content. So now I agree, such content is not appropriate for an AN about VREFBUF and indeed might be quite confusing. Still I think it is appropriate to include basic use cases (ADC, DAC), while highlighting e. g. the need of external capacitors as in this case, or the need to enable clock in the RCC. Or use this for a comparison with some standard bog LDO, as you suggest.

For the other points, I agree, thank you for pointing this out.

> 4.4

No problem. I would personally include this as an example for point 3 (where to use this reference voltage), and probably wouldn't go into such details...

> "how VRR is set"

Now, this is an interesting question. I checked with design and yes, when you cannot reach this expected voltage on *start-up*, it is not set. The boundaries are not +/-1 %, but -1/+1.5 %. However after VRR is set, it is latched until next power-down or voltage scaling change, so it cannot be used for such indication during the runtime.

> hold mode AN

No problem. I saw them, but as you mention, there is no additional value in those... And yes, as I have already stated, this mode should be IMO described more, ideally also with the diagram and examples you are suggesting.

> style of the ST documents

No, I cannot find any link like that, and even if I could, I wouldn't be able to share it to public for sure... This change was approved many years ago, maybe that is the main reason of that. For the same reason I do not know whose opinion was considered, sorry.

> datasheet values of capacitors

Low frequency cut-off capacitor is the one with 0.5-1.5 uF, but it requires another 100 nF capacitor to cut also the high frequency off. This is mentioned below VREFBUF characteristics, and also in the power supply diagram.

BR,

Jaroslav