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DAC DMA transfer size more than 65535?

AMagk.1
Associate II

My board is NUCLEO-H723ZG which has 1 DAC 2 channels built-in.

I actually want to transfer 2 arrays with 150,000 elements each in each DAC channel, but it is limited by the DMA size of 65535.

So, I have divided that array into 6 parts for example I_dac1, I_dac2 and I_dac3 and Q_dac1, Q_dac2, Q_dac3. I transmit both I_dac1 and Q_dac1 simultaneously to let it end at the same time.

When I_dac1 conversion is finished, I immediately use ConvCpltcallback like this

void HAL_DAC_HalfConvCpltCallbackCh1(dactypedef){

count++;

}

void HAL_DAC_ConvCpltCallbackCh1(dactypedef){

HAL_DAC_Stop_DMA(&hdac1, DAC_CHANNEL_1);

HAL_DAC_Stop_DMA(&hdac1, DAC_CHANNEL_2);

HAL_TIM_Base_Stop(&htim6);

if(count==1){

HAL_DAC_Start_DMA(&hdac1, DAC_CHANNEL_1, I_dac2, 8-bit alignment);

HAL_DAC_Start_DMA(&hdac1, DAC_CHANNEL_2, Q_dac2, 8-bit alignment);

HAL_TIM_Base_Start(&htim6);

}

else if(count==2){

HAL_DAC_Start_DMA(&hdac1, DAC_CHANNEL_1, I_dac3, 8-bit alignment);

HAL_DAC_Start_DMA(&hdac1, DAC_CHANNEL_2, Q_dac3, 8-bit alignment);

HAL_TIM_Base_Start(&htim6);

}

Then there is a ~10 us time gap between each of my count which is not acceptable in my application. The 10 us time gap mostly come from disabling both TIM and DAC but when I tried not to disable it, the signal in both channels doesn't come at the same time which is not acceptable as well.

How do I do?

Thank you in advance!

0693W00000WIG1YQAX.png

5 REPLIES 5
LCE
Principal

Check if that DMA supports double buffers (not sure if HAL does, so check reference manual and HAL functions), then use HALF complete DMA interrupt to set next DMA buffer source.

The half complete interrupts are available also on a single buffer DMAs/modes. Therefore double buffering can be implemented even on DMAs, which doesn't support double buffer mode. Using double buffer mode and half complete interrupts one can get 4 interrupts for a complete cycle.

I still have no idea with this solution, I already have all the data in the arrays I1, I2 and I3 and want to transmit these three arrays consecutively without any delay is this possible?

AScha.3
Chief

well, it would be much easier, ( if you do not work on top secret CIA project, ) just to tell:

  • what you wanna build
  • what it should do

on your NUCLEO-H723ZG board.

If you feel a post has answered your question, please click "Accept as Solution".
Piranha
Chief II

You don't have to stop the timer. Normal code register code can do DMA disable-enable much faster than the HAL broken bloatware. And with circular mode one can do continuous streaming, but that involves CPU, which has to move the data. If you can reduce the sample number to no more than 2*65535, then the dual buffer DMA can do it without the CPU.

Also the two DACs can be used in Dual DAC mode and fed from a single DMA.