2019-11-01 11:37 AM
What is it that I've been missing...
I set a timer to trig 7-channel ADC with DMA. The DMA is set to make 7 16-bit to 16-bit transfers circularly. It seemed to work fine, but some data started to corrupt. So I made the 7x16-bit buffer 4-fold (28 16-bit numbers) and it got half-written. It looks like the data is stored in two 7x16-bit blocks.
The actual doublebuffering was not used and the DMA_S0M1AR was zero.
(Checked in the Atollic debugger special register view.)
2019-11-02 02:48 AM
A bit off from the original question, but it seems that I haven't really gotten it...
What does NDTR count? I mean, if FIFO is used, the source is 8-bit and destination is 32-bit, what transfers does it count?
[edit]
Aha, AN4031 explains that for non-memory-to-memory case:
"The transfer size is defined by the DMA_SxNDTR register value and by the peripheral side data width".
2019-11-02 03:01 AM
Oh, I just realized, there is no hand written code involved. It's all generated by CubeMX.
Only the code in interrupt that copies the contents of the DMA buffer is hand-written, but should not be involved in this.
Maybe I can put the code here.
2019-11-02 04:13 AM
I started to wonder if this could be a timing problem. Maybe the clock triggering the ADC sweeps runs faster than intended. Could this happen, if new sweep is started before the previous one is properly finished?
2019-11-02 09:22 AM
Just came to my mind... how does MPU fit into the system? Is it also between the DMACs and memory? That is: can it trap illegal memory accesses by DMAC too? I suppose that the DMA peripheral buses are not seen by the MPU.
2019-11-02 11:28 AM
Speaking about timings.. Maybe DMA is delayed because of something other and ADC overrun happens. And, by the way, debugger breakpoints almost always cause ADC overrun.
2019-11-03 02:10 AM
Found it. It seems like the MPU is between the processor and the bus. It doesn't see what DMACs are doing. Should have guessed, because of the bus matrix...
2019-11-03 02:29 AM
I just don't see how ADC overrun could cause the "double buffering"-effect.
2019-11-03 02:31 AM
Maybe I should try with double buffering, but set both memory pointers to the same buffer, and see if that still happens...
2019-11-03 03:58 AM
On overrun interrupt code can restart capture sequence from the beginning, including DMA.
2019-11-03 04:08 AM
I'll check if there are overruns involved.