2025-08-30 3:18 PM - last edited on 2025-09-01 7:16 AM by Andrew Neil
Hello
I am trying to get the STMN32G431 processor to do what I want.
If I set the baudrates 500kB / 2MB and a samplepoint of 87.5% for both and send a CAN packet with FDF and BRS I get after 3 ms:
LastError = Recessive Bit Error and 8 Tx errors
and 2 ms later:
LastError = Recessive Bit Error, 248 Tx errors and Bus OFF !
Sometimes it is also a Dominant Bit Error.
This happens even in Internal loopback mode!
Therefore I set a Tx delay compensation of zero.
But also with other values for Tx delay compensation, it never works.
If I chose the samplepoint up to 85% all is still fine.
But with 87.5% I get a BusOff which is 100% reproducable.
Now comes the strange thing:
HAL_FDCAN_ConfigTxDelayCompensation(&can_handle, 0, 0);
HAL_FDCAN_EnableTxDelayCompensation(&can_handle);
will produce this problem, but with
HAL_FDCAN_DisableTxDelayCompensation(&can_handle);
it suddenly works correctly!
How is it possible that setting a delay of zero is not the same as a delay that is turned off?
Here my settings:
Clock 160 MHz
Nominal baudrate prescaler: 2
Segment 1 = 139
Segment 2 = 20
JSW = 8
Data baudrate prescaler: 5
Segment 1 = 13
Segment 2 = 2
JSW = 1
_____________________
Where can I find a documentation that explains in detail how to calculate the two values that I must pass to
HAL_FDCAN_ConfigTxDelayCompensation ?
I have been googling the whole day now and I have read the existing sparse documentation from ST and I still have absolutely no clue which values to pass to HAL_FDCAN_ConfigTxDelayCompensation ?
And as this compensates a hardware delay I also don't understand why must we not simply specify a fix delay in nanoseconds ?
If the CAN driver chip has a fix delay of 60 ns, I would expect a configuration where I enter 60 ns and that's it.
Why is this so complicated ?
And why is there no documentation how to calculate the values for offset and filter?
I found a posting that says to set the filter to zero and the offset to DataPrescaler * DataTimeSeg1.
But this does not work for 87.5%.
And it does not make sense to me.
The chip does not care about data segment 1.
The CAN bus transceiver chip has a fix hardware delay that never changes.
I would understand to calculate this delay from the clock frequency, but why from segment 1 ?
Can anybody explain me this in detail please?
2025-08-31 10:50 AM
The sample poin in the data phase is normaly set different then the sample point in the Arbitration phase (at about 50..70%). Also it is better to use the same prescaler for Arbitration and Data phase. Please read:
https://www.bosch-semiconductors.com/media/ip_modules/pdf_2/papers/icc14_2013_paper_hartwich_1.pdf
and
2025-09-01 6:04 AM
Hello,
1- Please watch this video on ST Youtube channel: FDCAN Normal Operating Mode
2- Use Kvaser online tool for FDCAN bit time computation. As said by @MHoll.2 , the sample point in data phase is not as for the arbitration phase and it tends to be in the middle of the bit instead of the end of it like with the arbitration phase (you can verify that using Kvaser tool).
3- You can also refer to this article as it may help you: STM32 FDCAN running at 8 Mb/s on NUCLEO boards
2025-09-01 7:13 AM
Probably by simply turning delay compensation on, there is a minimum delay in the used HW.
And in case of doubt, always check what the HAL functions actually do.
If the project is not just for hobby, you should know 100% what's going on.